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    Wedge-shaped high density capacitor and method of making the capacitor
    1.
    发明授权
    Wedge-shaped high density capacitor and method of making the capacitor 有权
    楔形高密度电容器和制造电容器的方法

    公开(公告)号：US06639784B1

    公开(公告)日：2003-10-28

    申请号：US10283810

    申请日：2002-10-30

    申请人： Peter Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang ,  Andy Strachan ,  Vladislav Vashchenko

    发明人： Peter Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang ,  Andy Strachan ,  Vladislav Vashchenko

    IPC分类号： H01J4228

    CPC分类号： H01L28/91 ,  H01L27/0805

    摘要： A capacitor structure is formed in a wedge-shaped trench by forming alternating layers of insulating material and conductive material in the trench such that each layer of conductive material formed in the trench is electrically isolated from adjacent layers of conductive material formed in the trench. A first electrical contact is formed to electrically link in parallel a first set of alternating layers of conductive material. A second electrical contact is formed to electrically link in parallel a second set of alternating layers of conductive material. The two electrically isolated sets of inter-linked layers of conductive material define the interdigitated capacitor structure.

    摘要翻译： 电容器结构通过在沟槽中形成绝缘材料和导电材料的交替层而形成在楔形沟槽中，使得形成在沟槽中的每个导电材料层与在沟槽中形成的导电材料的相邻层电隔离。 形成第一电接触以平行地电连接导电材料的第一组交替层。 形成第二电接触以平行地电连接第二组交替的导电材料层。 导电材料的两个电隔离的相互连接的层限定了交叉指向的电容器结构。

    On-chip power inductor
    2.
    发明授权
    On-chip power inductor 有权
    片上功率电感

    公开(公告)号：US07875955B1

    公开(公告)日：2011-01-25

    申请号：US11713921

    申请日：2007-03-05

    申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

    发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

    IPC分类号： H01L27/08

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F17/02 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor into the transistor array. Thus, the structure includes three basic components: a power inductor that spirals around the transistor array, the transistor array itself, and the transistor array metallization that is used to form a distributed inductance situated over the transistor array.

    摘要翻译： 用于DC-DC功率调节器电路的片上电感器结构将开关晶体管金属化与电感器并入。 用于绑定晶体管阵列并降低其导通电阻的厚顶级导体金属也用于将功率电感器扩展到晶体管阵列中。 因此，该结构包括三个基本部件：围绕晶体管阵列螺旋的功率电感器，晶体管阵列本身以及用于形成位于晶体管阵列上方的分布式电感器的晶体管阵列金属化。

    Method of inducing movement of charge carriers through a semiconductor material
    5.
    发明授权
    Method of inducing movement of charge carriers through a semiconductor material 有权
    引起载流子通过半导体材料的移动的方法

    公开(公告)号：US06660537B1

    公开(公告)日：2003-12-09

    申请号：US10219211

    申请日：2002-08-15

    申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang

    发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Kyuwoon Hwang

    IPC分类号： H01L2100

    CPC分类号： H01L31/103 ,  H01L27/14609 ,  H01L31/102

    摘要： A conductive trace is formed over and insulated from a region of semiconductor material, such as a region adjacent to the n+ region of an n+/p− photodiode, and a sawtooth current is made to flow through the conductive trace. The sawtooth current induces charge carriers to move through the semiconductor material to a collection region in the semiconductor material.

    摘要翻译： 导电迹线形成在与半导体材料的区域（例如与n + / p-型光电二极管的n +区域相邻的区域）之上并与之绝缘，并且使锯齿电流流过导电迹线。 锯齿电流引起电荷载流子移动通过半导体材料到半导体材料中的收集区域。

    Method of forming high lateral voltage isolation structure involving two separate trench fills
    6.
    发明授权
    Method of forming high lateral voltage isolation structure involving two separate trench fills 有权
    形成高横向电压隔离结构的方法，涉及两个单独的沟槽填充

    公开(公告)号：US08815700B2

    公开(公告)日：2014-08-26

    申请号：US12315934

    申请日：2008-12-08

    申请人： Peter J. Hopper ,  William French ,  Kyuwoon Hwang

    发明人： Peter J. Hopper ,  William French ,  Kyuwoon Hwang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76283

    摘要： In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

    摘要翻译： 在SOI工艺中，通过提供至少两个同心的电介质填充的沟槽来形成高横向电压隔离结构，去除介电填充的沟槽之间的半导体材料，并用电介质材料填充所得的间隙以限定单个宽的电介质填充的沟槽。

    METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS
    7.
    发明申请
    METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS 审中-公开
    改进射频电感器质量因子的方法和结构

    公开(公告)号：US20110272780A1

    公开(公告)日：2011-11-10

    申请号：US12774532

    申请日：2010-05-05

    申请人： Peter Smeys ,  Kyuwoon Hwang ,  Peter J. Hopper ,  William French

    发明人： Peter Smeys ,  Kyuwoon Hwang ,  Peter J. Hopper ,  William French

    IPC分类号： H01L29/86 ,  H01L21/02

    CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.

    摘要翻译： 片上电感器结构形成为集成电路结构的一部分。 集成电路结构包括具有顶侧和背面的半导体衬底，形成在衬底的顶侧上的集成电路元件，与集成电路元件接触形成的导电互连结构和形成在集成电路上的钝化层 元素。 电感器结构包括形成在钝化层上的可光成像环氧树脂层，形成在可光成像环氧树脂层上的导电电感线圈和从电感线圈延伸到互连层的至少一个导电通孔，以在它们之间提供电连接。 此外，可以在电感线圈下方的半导体衬底的背面形成背面沟槽。

    Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
    8.
    发明授权
    Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
    用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法

    公开(公告)号：US07897472B2

    公开(公告)日：2011-03-01

    申请号：US12624259

    申请日：2009-11-23

    申请人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

    发明人： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

    IPC分类号： H01L21/20

    CPC分类号： H01L23/645 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/19015 ,  H01L2924/19104 ,  H01L2924/00

    摘要： Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

    摘要翻译： 描述了在半导体晶片上形成多个电感器的方法。 将镀层和光致抗蚀剂层施加在半导体晶片上。 使用光刻技术在光致抗蚀剂层中蚀刻凹陷区域，其暴露下面的镀层的部分。 将金属电镀到光致抗蚀剂层的凹陷区域中以形成多个磁芯电感器构件。 介质绝缘层施加在磁芯电感器部件上。 在电介质绝缘层上施加附加的电镀和光致抗蚀剂层。 在新施加的光致抗蚀剂层中形成凹陷区域。 电镀用于在凹陷区域形成电感线圈。 可选地，可以在电感线圈上施加磁性糊。

    Method of forming high lateral voltage isolation structure involving two separate trench fills
    10.
    发明申请
    Method of forming high lateral voltage isolation structure involving two separate trench fills 有权
    形成高横向电压隔离结构的方法，涉及两个单独的沟槽填充

    公开(公告)号：US20100144116A1

    公开(公告)日：2010-06-10

    申请号：US12315934

    申请日：2008-12-08

    申请人： Peter J. Hopper ,  William French ,  Kyuwoon Hwang

    发明人： Peter J. Hopper ,  William French ,  Kyuwoon Hwang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76283

    摘要： In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

    摘要翻译： 在SOI工艺中，通过提供至少两个同心的电介质填充的沟槽来形成高横向电压隔离结构，去除介电填充的沟槽之间的半导体材料，并用电介质材料填充所得的间隙以限定单个宽的电介质填充的沟槽。