公开(公告)号：US4691435A

公开(公告)日：1987-09-08

申请号：US263227

申请日：1981-05-13

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  John L. Mauer, IV

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L21/385

CPC分类号： H01L29/872

摘要： A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

摘要翻译： 公开了用于在肖特基势垒二极管中制造小面积自对准保护环的方法。 垂直壁孔通过硅衬底上的电介质层完全各向异性地蚀刻。 掺杂多晶硅层沉积在有孔介电层上。 多晶硅被反射离子蚀刻掉，仅留下围绕电介质层中孔周边的衬里。 该结构被加热以将掺杂剂从衬里扩散到衬底中。 肖特基二极管金属沉积在通过介电层中的衬里孔暴露的衬底上。

公开(公告)号：US4389281A

公开(公告)日：1983-06-21

申请号：US217077

申请日：1980-12-16

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John S. Lechaton ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John S. Lechaton ,  James L. Walsh

IPC分类号： C01B33/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/76 ,  H01L21/306 ,  C03C15/00

CPC分类号： H01L21/31055 ,  H01L21/31116 ,  H01L21/312

摘要： The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.

摘要翻译： 本发明提供了一种平面化不均匀厚度的氧化物的方法，例如在集成电路中用于深介电隔离的氧化物填充沟槽上形成的二氧化硅。 通过平面化抗蚀剂蚀刻工艺去除氧化物，使得较厚抗蚀剂区域中的蚀刻以比较薄的抗蚀剂区域中的蚀刻速率慢。 所谓蚀刻剂是HF气体，蚀刻优选处于升高的温度。

公开(公告)号：US4196440A

公开(公告)日：1980-04-01

申请号：US909338

申请日：1978-05-25

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  Hans B. Pogge

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/08 ,  H01L29/735 ,  H01L29/06

CPC分类号： H01L27/0821 ,  H01L21/76232 ,  H01L29/735 ,  Y10S148/031 ,  Y10S148/051 ,  Y10S148/085

摘要： Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

摘要翻译： 描述了分离的单晶硅袋中的侧向PNP或NPN器件，其中二氧化硅隔离围绕该口袋并且部分地在该表面之下在隔离的单晶区域内。 P发射体或N发射体扩散在部分延伸到单晶隔离袋中的二氧化硅部分上进行。 这种结构减少了垂直电流注入，即使在低的基极 - 发射极电压下也将提供相对较高的（β）增益。

公开(公告)号：US4546536A

公开(公告)日：1985-10-15

申请号：US520365

申请日：1983-08-04

申请人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

发明人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L21/22 ,  H01L21/76 ,  H01L27/08

CPC分类号： H01L29/6625 ,  H01L21/743 ,  H01L21/8224 ,  H01L29/735 ,  Y10S148/01

摘要： The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ buried layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base a insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

摘要翻译： 描述了具有其基极宽度和晶体管的发射极区域最小化的横向晶体管。 横向晶体管的元件的这种最小化给出了高性能。 通常可以是PNP晶体管的横向晶体管形成在体内具有掩埋的N +区域的单晶半导体本体。 P型发射体区域位于体内。 N型基极区域位于发射极区域的侧边周围。 P型集电极区域位于围绕基极区域周边的主体中。 作为发射极区域的发射极接触点的第一P +多晶硅层与发射极区物理和电接触，并充当其电接触。 第二个P +多晶硅层位于主体的表面上，以与收集器区域物理和电接触。 在第二多晶硅层的边缘上的垂直绝缘体层将两个多晶硅层彼此隔离。 其表面的N基区位于垂直绝缘体层的宽度的下方。 从主体的表面向掩埋的N +区域延伸的N +通孔区域用作通过N +掩埋层到基极区域的电接触。 垂直绝缘体的宽度具有等于横向PNP晶体管的期望基极宽度以及横向PNP的集电极和发射极结的横向扩散的宽度。 优选的结构是使发射体形成在通道或槽的周边周围，该通道或槽在其底部具有诸如二氧化硅的绝缘层。 寄生晶体管几乎完全被这种掩埋氧化物隔离所消除。

公开(公告)号：US4492008A

公开(公告)日：1985-01-08

申请号：US520366

申请日：1983-08-04

申请人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

发明人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L27/08 ,  H01L21/76

CPC分类号： H01L29/6625 ,  H01L21/743 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/735

摘要： A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove. The P+ polycrystalline silicon layer is then formed on the surface which will in turn fill the groove with this material. The heating of the structure forms the P+ emitter region around the side edges of the P+ polycrystalline silicon filled groove. The P+ polycrystalline layer is the emitter contact, the N+ reach-through connected through the buried N+ region is the base contact and the collector contact is made to the P-type collector region.

摘要翻译： 可以通过首先提供具有主表面的单晶半导体主体并且其中期望的晶体管是PNP晶体管，具有将掩埋区域连接到所述主表面的N +到达通孔的掩埋N +区域来制造高性能横向晶体管。 晶体管的集电极区域通过将P型杂质铺展成期望的区域而形成为表面。 绝缘层形成在半导体本体的顶表面上。 在需要沟槽或沟道 - 发射极接触的绝缘层中形成开口。 使用图案化绝缘层作为蚀刻掩模，将基本垂直的壁槽蚀刻到单晶半导体本体中。 进行N基扩散以在体内的开口的周边周围产生N区。 然后将氧离子注入凹槽的底部，以在凹槽的底部形成二氧化硅区域。 然后在表面上形成P +多晶硅层，该表面依次用该材料填充凹槽。 结构的加热在P +多晶硅填充槽的侧边缘周围形成P +发射极区域。 P +多晶层是发射极接触，通过埋入N +区连接的N +到达通孔是基极接触，并且集电极接触到P型集电极区域。

公开(公告)号：US4389294A

公开(公告)日：1983-06-21

申请号：US279129

申请日：1981-06-30

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John L. Mauer, IV ,  Homi G. Sarkary

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  John L. Mauer, IV ,  Homi G. Sarkary

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  C23C15/00

CPC分类号： H01L21/76224 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76202 ,  Y10S438/978

摘要： A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30.degree. relative to the vertical direction of the sidewall.

摘要翻译： 用于消除已经被反应离子蚀刻的垂直二氧化硅侧壁上沉积的残留物（例如多晶硅残余物）的方法包括使侧壁重新形成相对于侧壁的垂直方向具有至少+ 30°的斜率。

公开(公告)号：US4316319A

公开(公告)日：1982-02-23

申请号：US141717

申请日：1980-04-18

申请人： Narasipur G. Anantha ,  Augustine W. Chang

发明人： Narasipur G. Anantha ,  Augustine W. Chang

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L27/08 ,  H01L29/8605 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/8222 ,  H01L21/743 ,  H01L27/0802 ,  H01L29/8605

摘要： A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

摘要翻译： 给出了一种用于高密度集成电路的高电阻结构及其制造方法。 该结构包括通过围绕该区域的介电阻挡层与其它硅区域分离的硅区域。 第一电导率的电阻器，例如N型，基本上包含硅区域的表面。 对电阻器进行电接触。 高度掺杂第二电导率的区域，例如P型，位于电阻区域的一部分的下方。 该第二导电区域连接到表面。 为了偏压目的，将电触头制成该变化区域。 可以将同一隔离硅区域内的第二区域用作电阻器。 该区域位于第二导电性的掩埋区域的下方。 或者，所描述的电阻器区域可以作为晶体管连接。 这允许形成标准的主机，其可以在制造的后期被个性化到标准区域的全部或一部分中的电阻器或晶体管。

公开(公告)号：UST101201I4

公开(公告)日：1981-11-03

申请号：US254039

申请日：1981-04-14

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia

IPC分类号： H01L21/033 ,  H01L21/3205 ,  H01L21/60 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/32051 ,  H01L29/475 ,  H01L29/872

摘要： Excessive leakage after initial forward stress, exhibited by subsequently reverse stressed nitride defined, Schottky barrier diodes is solved by the elimination of the "mouse hole" or undercut cavity in the oxide layer beneath the nitride ring defining the Schottky contact to the underlying silicon. The aforementioned cavity is filled by depositing chemical vapor deposited (CVD) oxide onto the nitride layer, into the nitride ring and the undercut oxide cavity beneath the ring and onto the underlying silicon substrate exposed through the nitride ring. The CVD oxide is then reactively ion etched to remove it except along the vertical walls of the nitride ring and the oxide cavity. The Schottky metal is deposited on the silicon substrate exposed by the reactive ion etching step.

公开(公告)号：US4427989A

公开(公告)日：1984-01-24

申请号：US293546

申请日：1981-08-14

申请人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

发明人： Narasipur G. Anantha ,  Harsaran S. Bhatia ,  Santosh P. Gaur ,  James L. Walsh

IPC分类号： G11C11/41 ,  G11C11/34 ,  G11C11/401 ,  H01L21/8229 ,  H01L27/102 ,  H01L27/115 ,  H01L29/74

CPC分类号： H01L27/1023 ,  G11C11/34 ,  H01L27/1028 ,  H01L27/115

摘要： A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

摘要翻译： 动态存储单元具有由N +层上的N层中的N +区包围的P +注入区。 喷射器区域放置在N +源极和漏极区域之间。 注入N层的孔被N +，N-界面处的高低接头捕获，并通过感测源极 - 漏极电流来检测。 当前级别用于在单元格中建立二进制一和零级。 对齐程序中的四个掩模简化了制造。

公开(公告)号：US4269631A

公开(公告)日：1981-05-26

申请号：US111570

申请日：1980-01-14

申请人： Narasipur G. Anantha ,  Gurumakonda R. Srinivasan

发明人： Narasipur G. Anantha ,  Gurumakonda R. Srinivasan

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/312 ,  H01L21/331 ,  H01L21/762 ,  H01L29/04 ,  H01L29/73 ,  H01L21/263 ,  H01L7/36

CPC分类号： H01L29/04 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/312 ,  H01L21/76248 ,  Y10S148/092 ,  Y10S148/123 ,  Y10S148/138

摘要： A method for making a filamentary pedestal transistor is disclosed in which epitaxial silicon is formed selectively above portions of a subcollector through the use of laser radiation. A single crystal substrate, having a subcollector of higher impurity concentration, is covered by an oxide mask which is apertured at two locations above the subcollector. Polycrystalline silicon is deposited over the apertured oxide mask. The structure is exposed to laser radiation of suitable energy level and wavelength to selectively convert the polycrystalline silicon to epitaxial monocrystalline silicon within and above the oxide apertures. The transistor is completed by conventional techniques to form base, emitter and collector reach-through regions.

摘要翻译： 公开了一种用于制造丝状基座晶体管的方法，其中通过使用激光辐射在子集电极的部分上选择性地形成外延硅。 具有较高杂质浓度的子集电极的单晶衬底由在子集电极上方的两个位置开孔的氧化物掩模覆盖。 在多孔氧化物掩模上沉积多晶硅。 该结构暴露于具有适当能级和波长的激光辐射以选择性地将多晶硅转化为氧化物孔内和之上的外延单晶硅。 晶体管通过常规技术完成，以形成基极，发射极和集电极贯通区域。