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    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
    5.
    发明申请
    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
    包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存

    公开(公告)号：US20150186275A1

    公开(公告)日：2015-07-02

    申请号：US14142045

    申请日：2013-12-27

    申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0888

    摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

    摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。

    ON-CHIP MESH INTERCONNECT
    9.
    发明申请
    ON-CHIP MESH INTERCONNECT 审中-公开
    芯片间网互连

    公开(公告)号：US20150006776A1

    公开(公告)日：2015-01-01

    申请号：US14126883

    申请日：2013-06-29

    申请人： Yen-Cheng Liu ,  Jason W. Horihan ,  Krishnakumar Ganapathy ,  Umit Y. Ogras ,  Allen W. Chu ,  Ganapati N. Srinivasa

    发明人： Yen-Cheng Liu ,  Jason W. Horihan ,  Krishnakumar Ganapathy ,  Umit Y. Ogras ,  Allen W. Chu ,  Ganapati N. Srinivasa

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4031 ,  G06F15/17381

    摘要： A particular message is received at a first ring stop connected to a first ring of a mesh interconnect including a plurality of rings oriented in a first direction and a plurality of rings oriented in a second direction substantially orthogonal to the first direction. The particular message is injected on a second ring of the mesh interconnect. The first ring is oriented in the first direction, the second ring is oriented in the second direction, and the particular message is to be forwarded on the second ring to another ring stop of a destination component connected to the second ring.

    摘要翻译： 在第一环路停止处接收特定的消息，该第一环路停止件连接到包括在第一方向上定向的多个环的网状互连的第一环和沿与第一方向大致正交的第二方向定向的多个环。 特定的消息被注入网状互连的第二个环上。 第一环在第一方向上定向，第二环在第二方向上定向，并且特定消息将在第二环上转发到连接到第二环的目的地组件的另一个环形停止。

    BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC
    10.
    发明申请
    BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC 审中-公开

    公开(公告)号：US20190236038A1

    公开(公告)日：2019-08-01

    申请号：US16227364

    申请日：2018-12-20

    申请人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    发明人： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    IPC分类号： G06F13/20 ,  G06F13/40

    CPC分类号： G06F13/20 ,  G06F13/4027

    摘要： Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes. The fabrics may comprise various topologies, including 2D mesh topologies and ring interconnect structures. Moreover, multi-level crediting and buffered mesh may be used for forwarding messages across dies.