-
1.发明授权Node processor for use with low density parity check decoder using multiple variable node degree distribution codes 有权节点处理器用于使用多个可变节点度分布码的低密度奇偶校验解码器公开(公告)号：US08261166B2
公开(公告)日：2012-09-04
申请号：US12212070
申请日：2008-09-17
申请人： Bengt A. Ulriksson
发明人： Bengt A. Ulriksson
IPC分类号： G06F11/00
CPC分类号： H03M13/1134 , H03M13/1111 , H03M13/6508
摘要： A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.
摘要翻译： 用于不同等级奇偶约束节点和高度并行处理的解码系统通过基于第一和第二校验节点的更新状态将消息传递到变量节点，处理来自变量节点的消息和更新第一和第二校验节点的状态来进行操作 具有并行操作的Z处理器的解码器，进一步处理用于第二校验节点的更新状态信息，以协调第二校验节点的N = Z / z组的状态，其中z是与第二校验节点相关联的位数， 并且使用第二校验节点的协调状态来重复该过程作为第二校验节点的更新状态。
-
公开(公告)号：US20110131444A1
公开(公告)日：2011-06-02
申请号：US12629481
申请日：2009-12-02
CPC分类号： G11C16/10 , G11C16/349
摘要： This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
摘要翻译： 本公开涉及固态存储器（例如闪速存储器）的低磨损操作的系统和方法。 在一个示例中，控制器耦合到存储器并且适于在数据存储设备的使用过程中动态地调整编程阈值，使得从存储在数据存储单元中的读取数据的信噪比不小于 使用增强的错误检测功能恢复数据所需的最小数量。
-
3.发明授权Parallel maximum a posteriori detectors that generate soft decisions for a sampled data sequence 有权并行最大后验检测器，为采样数据序列产生软判决公开(公告)号：US07555070B1
公开(公告)日：2009-06-30
申请号：US11045632
申请日：2005-01-28
申请人： Bengt A. Ulriksson , Rose Y. Shao
发明人： Bengt A. Ulriksson , Rose Y. Shao
CPC分类号： H03M13/3905 , H03M13/3972 , H03M13/6331 , H04L1/0054 , H04L1/0055
摘要： A soft decision value output detector includes a plurality of maximum a posteriori (MAP) detectors. The MAP detectors are connected in parallel, and configured to simultaneously generate state metrics for portions of a sampled data sequence, and to generate soft decision values based on the generated state metrics. The MAP detectors may generate soft decision values in a fixed latency manner and without buffering the sampled data sequence for a whole sector of a disk in a disk drive. The MAP detectors may generate soft decision values for portions of the sampled data sequence at least at a rate at which the portions of the sampled data sequence are input to the MAP detectors.
摘要翻译： 软判决值输出检测器包括多个最大后验（MAP）检测器。 MAP检测器并联连接，并且被配置为同时生成采样数据序列的部分的状态度量，并且基于生成的状态度量来生成软判决值。 MAP检测器可以以固定的等待时间方式生成软判决值，并且不缓冲磁盘驱动器中盘的整个扇区的采样数据序列。 MAP检测器可以至少以将采样数据序列的部分输入到MAP检测器的速率对采样数据序列的部分产生软判决值。
-
公开(公告)号：US07793201B1
公开(公告)日：2010-09-07
申请号：US11620400
申请日：2007-01-05
申请人： Bengt A. Ulriksson
发明人： Bengt A. Ulriksson
IPC分类号： H03M13/03
CPC分类号： H03M13/612 , H03M13/015 , H03M13/1111 , H03M13/3738
摘要： An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word. Alternatively, the system may group the bits into respective code word symbols and combine the bit error values into symbols-with-errors values using, for example, XOR sub-trees that produce, for each symbol, a single error value. The error value for a given symbol indicates that the symbol is either error-free or includes one or more bit errors, and a total count of the symbols with errors is produced by adding the error values together.
摘要翻译： 迭代解码器包括在相应的可变节点处，即在对应于码字的比特的节点处，在收敛之后的比特误差检测器确定相应的硬判决比特值是否已经从由信道提供的比特值改变。 给定位的值的变化表示位错误已被更正。 对于通过加法而不是乘法进行计算的消息传递解码器的位错误检测器可以容易地实现为异或门。 因此，通过对输入符号的符号位和可变节点和进行异或，在变量节点处检测到位错误。 在收敛之后，使用累加检测到的整个日期块或ECC码字的位错误的加法器树将由各个可变节点处的位错误检测器产生的输出值相加。 或者，系统可以将比特分组成相应的码字符号，并且使用例如针对每个符号产生单个误差值的异或子树来将比特误差值组合成具有错误值的符号。 给定符号的错误值表示符号是无错误的或包含一个或多个位错误，并且通过将错误值相加在一起产生具有错误的符号的总计数。
-
公开(公告)号：US07650561B1
公开(公告)日：2010-01-19
申请号：US11484462
申请日：2006-07-11
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/3707 , H03M13/3905 , H03M13/3966 , H03M13/3972
摘要： A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.
摘要翻译： MAP检测器系统以并行模式操作，用于实时操作和串行模式用于错误恢复操作。 在并行模式中，多个维特比运算符并行地处理一组输入采样数据。 在串行模式下，选择的前向维特比运算符和两个相关的反向维特比运算符按顺序处理整个数据块，以产生软判决数据。
-
公开(公告)号：US08130553B2
公开(公告)日：2012-03-06
申请号：US12629481
申请日：2009-12-02
CPC分类号： G11C16/10 , G11C16/349
摘要： This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
摘要翻译： 本公开涉及固态存储器（例如闪速存储器）的低磨损操作的系统和方法。 在一个示例中，控制器耦合到存储器并且适于在数据存储设备的使用过程中动态地调整编程阈值，使得从存储在数据存储单元中的读取数据的信噪比不小于 使用增强的错误检测功能恢复数据所需的最小数量。
-
7.发明申请NODE PROCESSOR FOR USE WITH LOW DENSITY PARITY CHECK DECODER USING MULTIPLE VARIABLE NODE DEGREE DISTRIBUTION CODES 有权使用多个可变节点分配码的低密度奇偶校验解码器的节点处理器公开(公告)号：US20100070818A1
公开(公告)日：2010-03-18
申请号：US12212070
申请日：2008-09-17
申请人： Bengt A. Ulriksson
发明人： Bengt A. Ulriksson
CPC分类号： H03M13/1134 , H03M13/1111 , H03M13/6508
摘要： A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.
摘要翻译： 用于不同等级奇偶约束节点和高度并行处理的解码系统通过基于第一和第二校验节点的更新状态将消息传递到变量节点，处理来自变量节点的消息和更新第一和第二校验节点的状态来进行操作 具有并行操作的Z处理器的解码器，进一步处理用于第二校验节点的更新状态信息，以协调第二校验节点的N = Z / z组的状态，其中z是与第二校验节点相关联的位数， 并且使用第二校验节点的协调状态来重复该过程作为第二校验节点的更新状态。
-
公开(公告)号：US4682060A
公开(公告)日：1987-07-21
申请号：US708494
申请日：1985-03-05
CPC分类号： G01R29/26 , H03D1/2245 , H03D7/166
摘要： In an I-F substitution loop having a summing junction for receiving both an I-F signal and a substitution signal, an amplification loop is connected in parallel with the substitution loop for amplifying and bandpass filtering the signal at the summing junction, and feeding back to the summing junction the processed summing junction signal, for reducing the phase noise at the summing junction.
摘要翻译： 在具有用于接收IF信号和替代信号两者的求和点的IF取代环路中，放大环路与替代环路并联连接，用于放大和对滤波器进行带通滤波，并将其馈送到求和点 处理的求和结信号，用于降低求和点处的相位噪声。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.01 秒)
