公开(公告)号：US4800543A

公开(公告)日：1989-01-24

申请号：US128550

申请日：1987-12-03

申请人： Ross Lyndon-James ,  Alfred P. Gnadinger ,  Donald L. Black ,  Carlos P. de Araujo

发明人： Ross Lyndon-James ,  Alfred P. Gnadinger ,  Donald L. Black ,  Carlos P. de Araujo

IPC分类号： G04C3/00 ,  G04G21/04 ,  G04G99/00 ,  G06K17/00 ,  G07C9/00 ,  G07F7/02 ,  G07F7/08 ,  G07F7/10 ,  G07G1/00 ,  H04Q9/00 ,  G04B47/00

CPC分类号： G04G21/04 ,  G06Q20/206 ,  G07C9/00111 ,  G07F7/02 ,  G07F7/1008 ,  G07F7/1025 ,  G07G1/0036

摘要： A wristwatch contains communication and memory circuitry and a transmitter. The memory circuit stores a personal identification number of a single user. The communication and memory circuitry is driven by the same battery which powers the timekeeping structure of the watch. A transmitter transmits data from the reader to the wristwatch, placed proximate thereto. The reader has a keypad by which the user can enter a personal identification number, and the watch compares the transmitted number to the user-entered number. If the numbers match, a transaction may occur.

公开(公告)号：US5466629A

公开(公告)日：1995-11-14

申请号：US383575

申请日：1995-02-03

申请人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

发明人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/60 ,  H01L28/55

摘要： An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.

摘要翻译： 超大型铁电电容器位于DRAM中的MOSFET源极/漏极的接触孔处。 在铁电层和源极漏极之间，由氮化钛，钛钨，钽，钛，钨，钼，铬，氧化铟锡，二氧化锡，氧化钌，硅，硅化物或多晶硅化物形成的阻挡层。 阻挡层可以用作铁电电容器的底部电极，或者可以使用由铂制成的单独的底部电极。 在其中阻挡层形成底部电极的另一个实施例中，小于5nm厚的氧化物层位于势垒层和铁电层之间，阻挡层由硅，硅化物或多硅化物制成。 薄的硅化物层在阻挡层和源极/漏极之间形成欧姆接触。 在单个掩模步骤中对电容器和阻挡层进行图案化。 电容器的端部是阶梯式或锥形的。 在另一个实施例中，底部和顶部电极可以由硅，硅化物，多晶硅或导电氧化物，例如氧化铟锡，二氧化锡或氧化钌制成。

公开(公告)号：US5561307A

公开(公告)日：1996-10-01

申请号：US276474

申请日：1994-07-18

申请人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

发明人： Takashi Mihara ,  Hiroyuki Yoshimori ,  Hitoshi Watanabe ,  Larry D. McMillan ,  Carlos P. De Araujo

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  C23C14/00 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/60 ,  H01L28/55

摘要： An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.

摘要翻译： 超大型铁电电容器位于DRAM中的MOSFET源极/漏极的接触孔处。 在铁电层和源极漏极之间，由氮化钛，钛钨，钽，钛，钨，钼，铬，氧化铟锡，二氧化锡，氧化钌，硅，硅化物或多晶硅化物形成的阻挡层。 阻挡层可以用作铁电电容器的底部电极，或者可以使用由铂制成的单独的底部电极。 在其中阻挡层形成底部电极的另一个实施例中，小于5nm厚的氧化物层位于势垒层和铁电层之间，阻挡层由硅，硅化物或多硅化物制成。 薄的硅化物层在阻挡层和源极/漏极之间形成欧姆接触。 在单个掩模步骤中对电容器和阻挡层进行图案化。 电容器的端部是阶梯式或锥形的。 在另一个实施例中，底部和顶部电极可以由硅，硅化物，多晶硅或导电氧化物，例如氧化铟锡，二氧化锡或氧化钌制成。