公开(公告)号：US20090140429A1

公开(公告)日：2009-06-04

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

公开(公告)号：US20080258288A1

公开(公告)日：2008-10-23

申请号：US12148404

申请日：2008-04-18

Applicant: Jin-woo Park ,  Cha-je Jo ,  Eun-chul Ahn ,  Tae-joo Hwang ,  Hae-jung Yu ,  Chan Park

Inventor： Jin-woo Park ,  Cha-je Jo ,  Eun-chul Ahn ,  Tae-joo Hwang ,  Hae-jung Yu ,  Chan Park

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/73 ,  H01L24/12 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a semiconductor device stack package and a method of forming the same, the package comprises: a substrate; a plurality of lower chips stacked on the substrate and having an active surface oriented in a direction toward the substrate; and at least one upper chip disposed on the lower chips and connected to the substrate via a bump disposed between the lower chips. As no wire loops are formed, there is no increase in the height of the stack package, and the electrical path is shortened, thereby improving the electric performance of the stack package. Also, the semiconductor device stack package has a flip chip structure, and thus a plurality of semiconductor chips can be stacked in various manners.

Abstract translation: 在半导体器件堆叠封装及其形成方法中，封装包括：衬底; 堆叠在所述基板上并具有朝向所述基板的方向取向的有源面的多个下部芯片; 以及设置在下芯片上的至少一个上芯片，并且经由设置在下芯片之间的凸块连接到基板。 由于没有形成线环，堆叠封装的高度没有增加，并且电路被缩短，从而提高了堆叠封装的电性能。 此外，半导体器件堆叠封装具有倒装芯片结构，因此可以以各种方式堆叠多个半导体芯片。

公开(公告)号：US07960273B2

公开(公告)日：2011-06-14

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。