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    Metal interconnection of a semiconductor device and method of manufacturing the same
    1.
    发明申请
    Metal interconnection of a semiconductor device and method of manufacturing the same 有权
    半导体器件的金属互连及其制造方法

    公开(公告)号：US20090140429A1

    公开(公告)日：2009-06-04

    申请号：US12292827

    申请日：2008-11-26

    Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

    Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

    Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

    Metal interconnection of a semiconductor device and method of manufacturing the same
    2.
    发明授权
    Metal interconnection of a semiconductor device and method of manufacturing the same 有权
    半导体器件的金属互连及其制造方法

    公开(公告)号：US07960273B2

    公开(公告)日：2011-06-14

    申请号：US12292827

    申请日：2008-11-26

    Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

    Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

    IPC: H01L21/44 ,  H01L21/4763

    CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

    Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

    Method for manufacturing circuit board
    3.
    发明授权
    Method for manufacturing circuit board 失效
    电路板制造方法

    公开(公告)号：US08418355B2

    公开(公告)日：2013-04-16

    申请号：US11976071

    申请日：2007-10-19

    Applicant: Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

    Inventor： Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

    IPC: H05K3/20

    CPC classification number: H05K3/20 ,  H05K3/205 ,  H05K3/207 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49163

    Abstract: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.

    Abstract translation: 公开了一种形成转录电路的方法及其制造方法。 一种形成转录电路的方法，其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案，将导电材料填充到凹版图案中，以及通过将载体压载到载体上而将载体转移到 使得载体面向具有填充有导电材料的模板的表面的模板，使得可以形成可以使用现有设备转录成绝缘板的转录电路，由此可以降低成本。

    APPARATUS AND METHOD FOR TREATING SUBSTRATE
    4.
    发明申请
    APPARATUS AND METHOD FOR TREATING SUBSTRATE 审中-公开
    用于处理基板的装置和方法

    公开(公告)号：US20110226626A1

    公开(公告)日：2011-09-22

    申请号：US13039822

    申请日：2011-03-03

    Applicant: Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

    Inventor： Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

    IPC: C25D5/48 ,  H01L21/306

    CPC classification number: H01L21/6723 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/6719 ,  H01L21/68728 ,  H01L21/68785

    Abstract: A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion.

    Abstract translation: 基板处理装置可以包括：电镀处理部，被配置为进行基板的电镀处理;湿处理部，被配置为进行基板的湿式处理;湿处理部位于电镀处理部下;以及基板支撑 被配置为支撑所述基板的部分，使得所述基板的电镀表面面向上，所述基板支撑部分还被配置为在所述电镀处理部分和所述湿处理部分之间移动所述基板。

    Optical device including gate insulating layer having edge effect
    7.
    发明授权
    Optical device including gate insulating layer having edge effect 有权
    光学器件包括具有边缘效应的栅极绝缘层

    公开(公告)号：US07924492B2

    公开(公告)日：2011-04-12

    申请号：US12374261

    申请日：2007-04-24

    Applicant: Hyun-Soo Kim ,  Jeong-Woo Park ,  Bongki Mheen ,  Young-Ahn Leem ,  Gyungock Kim

    Inventor： Hyun-Soo Kim ,  Jeong-Woo Park ,  Bongki Mheen ,  Young-Ahn Leem ,  Gyungock Kim

    IPC: G02F1/07

    CPC classification number: G02F1/025 ,  G02F2203/50 ,  G11C13/04

    Abstract: Provided is an optical device having an edge effect with improved phase shift and propagation loss of light without decreasing the dynamic characteristics of the optical device. The optical device includes a first semiconductor layer which is doped with a first type of conductive impurities, and has a recessed groove in an upper portion thereof; a gate insulating layer covering the groove and a portion of the first semiconductor layer; and a second semiconductor layer which covers an upper surface of the gate insulating layer and is doped with a second type of conductive impurities opposite to the first type of conductive impurities.

    Abstract translation: 提供一种具有边缘效应的光学器件，具有改善的相移和光的传播损耗，而不会降低光学器件的动态特性。 光学器件包括掺杂有第一类导电杂质的第一半导体层，并且在其上部具有凹槽; 覆盖所述沟槽和所述第一半导体层的一部分的栅极绝缘层; 以及覆盖所述栅极绝缘层的上表面并且掺杂有与所述第一类型的导电杂质相反的第二类导电杂质的第二半导体层。

    Photoelectric device using PN diode and silicon integrated circuit (IC) including the photoelectric device
    9.
    发明授权
    Photoelectric device using PN diode and silicon integrated circuit (IC) including the photoelectric device 失效
    光电器件采用PN二极管和硅集成电路（IC），包括光电器件

    公开(公告)号：US08346026B2

    公开(公告)日：2013-01-01

    申请号：US12517802

    申请日：2007-08-07

    Applicant: Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

    Inventor： Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

    IPC: G02F1/035 ,  G02B6/12 ,  G02B6/00

    CPC classification number: H01L31/12 ,  H01L27/144

    Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.

    Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路（IC）。 光电装置包括：基板; 以及在所述衬底上形成为PN二极管的光波导，其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极，其中PN二极管的N型和P型半导体以高浓度掺杂，并且N型半导体的掺杂浓度高于或等于P 型半导体。

    APPARATUS AND METHOD FOR ELECTROPLATING FOR SEMICONDUCTOR SUBSTRATE
    10.
    发明申请
    APPARATUS AND METHOD FOR ELECTROPLATING FOR SEMICONDUCTOR SUBSTRATE 审中-公开
    用于半导体基板电镀的装置和方法

    公开(公告)号：US20120292195A1

    公开(公告)日：2012-11-22

    申请号：US13438020

    申请日：2012-04-03

    Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

    Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

    IPC: C25B15/00 ,  C25B9/00

    CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

    Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

    Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

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