公开(公告)号：US20090140429A1

公开(公告)日：2009-06-04

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

公开(公告)号：US07960273B2

公开(公告)日：2011-06-14

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

公开(公告)号：US09793165B2

公开(公告)日：2017-10-17

申请号：US13345441

申请日：2012-01-06

Applicant: Seyoung Jeong ,  Taeje Cho ,  Hogeon Song ,  Kyu-Ha Lee

Inventor： Seyoung Jeong ,  Taeje Cho ,  Hogeon Song ,  Kyu-Ha Lee

IPC: H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05109 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.

公开(公告)号：US20150243637A1

公开(公告)日：2015-08-27

申请号：US14709840

申请日：2015-05-12

Applicant: Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L25/065 ,  G11C8/00 ,  G11C16/08 ,  H01L23/544

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。

公开(公告)号：US20060164970A1

公开(公告)日：2006-07-27

申请号：US11063125

申请日：2005-02-22

Applicant: Kyu-Ha Lee ,  Sung-Hun Jung ,  Dae-Sik Hong ,  Eun-Seok Ko ,  Jae-Hee Cho

Inventor： Kyu-Ha Lee ,  Sung-Hun Jung ,  Dae-Sik Hong ,  Eun-Seok Ko ,  Jae-Hee Cho

IPC: H04J11/00 ,  H04J3/02

CPC classification number: H04B7/0891 ,  H04B7/06 ,  H04L27/2608

Abstract: A transmitter of a Diagonal Bell Laboratories Layered Space-Time (DBLAST) system includes an interleaver for performing interleaving for all sub-streams in a stream of a transmission signal, thereby generating an interleaved signal, a symbol repeater for generating a reverse-arranged signal rearranged in a reverse order to the interleaved signal, and a DBLAST transmit unit for transmitting the interleaved signal and the reverse-arranged signal through multiple transmit antennas. A receiver of a DBLAST system includes a DBLAST receive unit for receiving signals through multiple transmit antennas, a repeating symbol combiner for generating a combined signal; a deinterleaver for generating a deinterleaved signal; and a decoder for decoding the deinterleaved signal.

Abstract translation: 对角贝尔实验室分层时空（DBLAST）系统的发射机包括交织器，用于对传输信号的流中的所有子流执行交织，从而产生交织的信号，用于产生反向排列的信号的符号中继器 以与交错信号相反的顺序重新排列，以及DBLAST发送单元，用于通过多个发送天线发送交织信号和反向排列的信号。 DBLAST系统的接收机包括用于通过多个发射天线接收信号的DBLAST接收单元，用于产生组合信号的重复符号组合器; 用于产生解交织信号的解交织器; 以及用于对解交错信号进行解码的解码器。

公开(公告)号：US20050280564A1

公开(公告)日：2005-12-22

申请号：US10951249

申请日：2004-09-27

Applicant: Kyu-Ha Lee

Inventor： Kyu-Ha Lee

IPC: H03H17/02 ,  H03H17/06 ,  H03M7/00

CPC classification number: H03H17/0671

Abstract: Disclosed is a digital sampling rate converter for compensating for a drop of an in-band signal, the digital sampling rate converter including a CIC (Cascaded Integrator-Comb) decimator for performing a decimation operation at a first decimation ratio based on an overall decimation ratio, for an input signal; a sub-decimator for performing a decimation operation at a second decimation ratio for a signal output from the CIC decimator; and a compensation unit for performing at least two multiplication operations and two addition operations with respect to a signal output from the sub-decimator using a lowest operation clock frequency in an assigned band.

Abstract translation: 公开了一种数字采样率转换器，用于补偿带内信号的下降，该数字采样率转换器包括一个CIC（级联积分 - 梳状）抽取器，用于基于总抽取比率以第一抽取比率执行抽取运算 ，用于输入信号; 用于对从CIC抽取器输出的信号执行第二抽取比例的抽取操作的子抽取器; 以及补偿单元，用于使用分配频带中的最低操作时钟频率来执行关于从子抽取器输出的信号的至少两个乘法运算和两个相加运算。

公开(公告)号：US08114772B2

公开(公告)日：2012-02-14

申请号：US12906578

申请日：2010-10-18

Applicant: Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Ii Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

Inventor： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Ii Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

Abstract translation: 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US20110097891A1

公开(公告)日：2011-04-28

申请号：US12906578

申请日：2010-10-18

Applicant: Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

Inventor： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

Abstract translation: 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US08778776B2

公开(公告)日：2014-07-15

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US20140179103A1

公开(公告)日：2014-06-26

申请号：US14108771

申请日：2013-12-17

Applicant: Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

Inventor： Pil-Kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Jumyong Park ,  Jinho Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gilheyun Choi

IPC: H01L21/768

CPC classification number: H01L25/0657 ,  G11C8/00 ,  G11C16/08 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13169 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed.

Abstract translation: 提供半导体器件的导电通孔，其沿垂直方向穿过衬底延伸，导电通孔的第一端延伸穿过衬底的第一表面，使得第一端相对于衬底的第一表面在垂直方向上突出 底物。 绝缘层设置在导电通孔的第一端和基板的第一表面上。 除去掩模层图案的上部，使得在导电通孔的第一端上的绝缘层的封盖部分露出。 去除绝缘层的与导电通孔相隔一定距离的一部分，以在绝缘层中形成凹陷。 同时去除导电通孔第一端上的绝缘层的封盖部分。