公开(公告)号：US08952543B2

公开(公告)日：2015-02-10

申请号：US13718580

申请日：2012-12-18

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Gil-Heyun Choi

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

Abstract translation: 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US08941972B2

公开(公告)日：2015-01-27

申请号：US13572407

申请日：2012-08-10

Applicant: Myung Jun Park ,  Sang Hoon Kwon ,  Chang Hoon Kim ,  Hyun Hee Gu ,  Jae Young Park ,  Da Young Choi ,  Kyu Ha Lee ,  Byung Jun Jeon

Inventor： Myung Jun Park ,  Sang Hoon Kwon ,  Chang Hoon Kim ,  Hyun Hee Gu ,  Jae Young Park ,  Da Young Choi ,  Kyu Ha Lee ,  Byung Jun Jeon

IPC: H01G4/30 ,  H01B3/12 ,  H01G4/12 ,  H01G4/232

CPC classification number: H01B3/12 ,  H01G4/12 ,  H01G4/2325 ,  H01G4/30 ,  Y10T29/417

Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same. The multilayer ceramic electronic component includes: a ceramic body including a dielectric layer; first and second internal electrodes disposed within the ceramic body to face each other, while having the dielectric layer interposed therebetween; and first external electrodes electrically connected to first and second internal electrodes and second external electrodes formed on the first external electrodes, wherein the first and second external electrodes include a conductive metal and a glass, and when the second external electrodes are divided into three equal parts in a thickness direction, an area of the glass in central parts thereof with respect to an area of the central parts is 30 to 80%. Therefore, sealing properties of a chip is improved, whereby a multilayer ceramic electronic component having improved reliability may be implemented.

Abstract translation: 提供了一种多层陶瓷电子部件及其制造方法。 多层陶瓷电子部件包括：陶瓷体，其包括电介质层; 第一和第二内部电极设置在陶瓷体内以彼此面对，同时介于其间的电介质层; 以及第一外部电极，电连接到形成在第一外部电极上的第一和第二内部电极和第二外部电极，其中第一和第二外部电极包括导电金属和玻璃，并且当第二外部电极被分成三个相等部分 在厚度方向上，中央部分的玻璃的面积相对于中央部的面积为30〜80％。 因此，提高了芯片的密封性，可以实现具有提高的可靠性的多层陶瓷电子部件。

公开(公告)号：US08941971B2

公开(公告)日：2015-01-27

申请号：US13569703

申请日：2012-08-08

Applicant: Myung Jun Park ,  Kyu Ha Lee ,  Da Young Choi ,  Chang Hoon Kim ,  Hyun Hee Gu ,  Jae Young Park ,  Sang Hoon Kwon ,  Byung Jun Jeon

Inventor： Myung Jun Park ,  Kyu Ha Lee ,  Da Young Choi ,  Chang Hoon Kim ,  Hyun Hee Gu ,  Jae Young Park ,  Sang Hoon Kwon ,  Byung Jun Jeon

IPC: H01G4/30

CPC classification number: H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H01G4/2325

Abstract: There are provided a multilayer ceramic electronic component comprising: a ceramic main body including a dielectric layer and having first and second main faces, third and fourth side faces opposed in a length direction, and fifth and sixth faces opposed in a width direction; first and second internal electrodes; and one or more first external electrodes formed on the fifth face and one or more second external electrodes formed on the sixth face, wherein the first and second external electrodes have an average thickness ranging from 3 μm to 30 μm, and when at least one of the first and second external electrodes is divided into three equal parts in a thickness direction, an area of glass in central area portions thereof is 35% to 80% of the total areas of the central area portions.

Abstract translation: 提供了一种多层陶瓷电子部件，包括：陶瓷主体，包括电介质层，具有第一和第二主面，沿长度方向相对的第三和第四侧面以及沿宽度方向相对的第五和第六面; 第一和第二内部电极; 以及形成在第五面上的一个或多个第一外部电极和形成在第六面上的一个或多个第二外部电极，其中第一外部电极和第二外部电极具有3μm至30μm的平均厚度，并且当至少一个 第一外部电极和第二外部电极在厚度方向上分成三个相等的部分，其中心区域部分的玻璃面积为中心区域部分总面积的35％至80％。

公开(公告)号：US08767375B2

公开(公告)日：2014-07-01

申请号：US13569738

申请日：2012-08-08

Applicant: Myung Jun Park ,  Sang Hoon Kwon ,  Jae Young Park ,  Kyu Ha Lee ,  Byung Jun Jeon ,  Da Young Choi ,  Hyun Hee Gu ,  Chang Hoon Kim

Inventor： Myung Jun Park ,  Sang Hoon Kwon ,  Jae Young Park ,  Kyu Ha Lee ,  Byung Jun Jeon ,  Da Young Choi ,  Hyun Hee Gu ,  Chang Hoon Kim

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/005 ,  H01G4/12

CPC classification number: H01G4/228 ,  H01G4/005 ,  H01G4/12 ,  H01G4/30

Abstract: There are provided a multilayer ceramic electronic component, and a method of fabricating the same. The multilayer ceramic electronic component includes: a ceramic main body including a dielectric layer; first and second internal electrodes disposed to face each other within the ceramic main body; and a first external electrode and a second external electrode, wherein the first and second external electrodes include a conductive metal and glass, and when at least one of the first and second external electrodes is divided into three equal parts in a thickness direction, an area of the glass in a central part thereof is 35% to 80% of the total area of the central part. A multilayer ceramic electronic component having improved reliability may be implemented by enhancing chip air-tightness.

Abstract translation: 提供了一种多层陶瓷电子部件及其制造方法。 多层陶瓷电子部件包括：陶瓷主体，其包括电介质层; 第一和第二内部电极，其设置成在陶瓷主体内彼此面对; 以及第一外部电极和第二外部电极，其中所述第一和第二外部电极包括导电金属和玻璃，并且当所述第一外部电极和所述第二外部电极中的至少一个在厚度方向上被分成三个相等的部分时， 的中心部分的玻璃的总面积的35％至80％。 具有提高的可靠性的多层陶瓷电子部件可以通过提高芯片气密性来实现。

公开(公告)号：US08564139B2

公开(公告)日：2013-10-22

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20130134603A1

公开(公告)日：2013-05-30

申请号：US13610068

申请日：2012-09-11

Applicant: Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Seokho Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L23/48

CPC classification number: H01L23/3192 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

Abstract: Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern.

Abstract translation: 提供半导体器件及其制造方法。 所述器件可以包括半导体衬底，设置在所述半导体衬底中以在所述半导体衬底的表面电平处具有第一宽度的第一导电图案，覆盖所述第一导电图案并具有基本上大于所述第一宽度的第二宽度的阻挡图案 ，部分地覆盖所述阻挡图案并且具有基本上小于所述第二宽度的第三宽度的第二导电图案，以及设置在所述第二导电图案的侧壁上的绝缘图案。 第二宽度可以基本上等于或小于绝缘图案的第三宽度和宽度之和。

公开(公告)号：US20120295122A1

公开(公告)日：2012-11-22

申请号：US13353010

申请日：2012-01-18

Applicant: Myung Jun PARK ,  Da Young Choi ,  Byong Gyun Kim ,  Ji Sook Kim ,  Byung Jun Jeon ,  Hyun Hee Gu ,  Kyu Ha Lee ,  Gun Jung Yoon ,  Eun Sang Na

Inventor： Myung Jun PARK ,  Da Young Choi ,  Byong Gyun Kim ,  Ji Sook Kim ,  Byung Jun Jeon ,  Hyun Hee Gu ,  Kyu Ha Lee ,  Gun Jung Yoon ,  Eun Sang Na

IPC: B32B15/04

CPC classification number: C03C3/00 ,  B32B18/00 ,  C03C3/066 ,  C03C3/089 ,  C03C8/04 ,  C04B2237/346 ,  C04B2237/68 ,  C22C19/03

Abstract: There is provided a multilayered ceramic electronic component having a reduced thickness and exhibiting hermetic sealing. In multilayered ceramic electronic component, an external electrode includes two layers, that is, first and second layers, and the first and second layers contain glass with different compositions, respectively. Therefore, the multilayered ceramic electronic component having high reliability, such as strong adhesion between the external electrode and the internal electrode, prevention of glass exudation, or the like, may be obtained.

Abstract translation: 提供了具有减小的厚度并呈现气密密封的多层陶瓷电子部件。 在多层陶瓷电子部件中，外部电极包括两层，即第一层和第二层，第一层和第二层分别含有不同组成的玻璃。 因此，可以获得具有高可靠性的多层陶瓷电子部件，例如外部电极和内部电极之间的强粘合性，防止玻璃渗出等。

公开(公告)号：US20120154977A1

公开(公告)日：2012-06-21

申请号：US13111319

申请日：2011-05-19

Applicant: Kang Heon HUR ,  Chang Hoon KIM ,  Sung Bum SOHN ,  Ji Sook KIM ,  Hyun Hee GU ,  Gun Jung YOON ,  Kyu Ha LEE ,  Sang Hoon KWON ,  Myung Jun PARK

Inventor： Kang Heon HUR ,  Chang Hoon KIM ,  Sung Bum SOHN ,  Ji Sook KIM ,  Hyun Hee GU ,  Gun Jung YOON ,  Kyu Ha LEE ,  Sang Hoon KWON ,  Myung Jun PARK

IPC: H01G4/008 ,  B32B38/10 ,  B32B37/06 ,  B32B37/14 ,  H01B1/16 ,  B32B37/02

CPC classification number: H01G4/2325 ,  H01B1/16 ,  H01G4/30

Abstract: There are provided a conductive paste composition for a termination electrode, a multilayer ceramic capacitor having the same, and a method thereof. The conductive paste composition for a termination electrode includes a conductive metal powder and a glass frit represented by the following Formula: aSiO2-bB2O3-cAl2O3-dTMxOy-eR12O-fR2O, where TM is a transition metal selected from a group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe) and nickel (Ni); R1 is selected from a group consisting of lithium (Li), sodium (Na) and potassium (K); R2 is selected from a group consisting of magnesium (Mg), calcium (Ca), strontium (Sr) and barium (Ba); each of x and y is larger than 0; and ‘a’ ranges from 15 to 70 mol %, ‘b’ ranges from 15 to 45 mol %, ‘c’ ranges from 1 to 10 mol %, ‘d’ ranges from 1 to 50 mol %, ‘e’ ranges from 2 to 30 mol % and ‘f’ ranges from 5 to 40 mol %. The conductive paste composition for a termination electrode includes a glass frit compound having improved corrosion resistance to a plating solution, thus effectively preventing the penetration of the plating solution and enhancing chip reliability.

Abstract translation: 提供了一种终端电极用导电性糊剂组合物及其制造方法。 用于终端电极的导电糊组合物包括导电金属粉末和由下式表示的玻璃料：aSiO 2 -BB 2 O 3 -cAl 2 O 3-d TM x O y e e 12 O-f R 2 O，其中TM是选自锌（Zn ），钛（Ti），铜（Cu），钒（V），锰（Mn），铁（Fe）和镍（Ni） R1选自锂（Li），钠（Na）和钾（K）组成的组中; R2选自镁（Mg），钙（Ca），锶（Sr）和钡（Ba）组成的组中; x和y各自大于0; 'a'为15〜70摩尔％，'b'为15〜45摩尔％，'c'为1〜10摩尔％，'d'为1〜50摩尔％，'e' 2〜30摩尔％，'f'为5〜40摩尔％。 用于端接电极的导电糊剂组合物包括具有改善的对电镀溶液的耐腐蚀性的玻璃料化合物，从而有效地防止了电镀液的渗透并提高了芯片的可靠性。

公开(公告)号：US20120083097A1

公开(公告)日：2012-04-05

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US07960273B2

公开(公告)日：2011-06-14

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。