公开(公告)号：US20090167399A1

公开(公告)日：2009-07-02

申请号：US12123613

申请日：2008-05-20

申请人： Hung-Wen LU ,  Chau-Chin SU

发明人： Hung-Wen LU ,  Chau-Chin SU

IPC分类号： H03H11/26

CPC分类号： H03H11/26 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00228 ,  H03K2005/00234

摘要： A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

摘要翻译： 描述包括电容性负载元件的信号延迟电路。 电容性负载元件具有第一输入端，第二输入端和第三输入端。 第一输入端接收第一信号，第二输入端接收到与第一信号反相的第二信号，第三输入端接收控制信号。 容性负载元件的电容随控制信号而变化。

公开(公告)号：US20050207520A1

公开(公告)日：2005-09-22

申请号：US10800653

申请日：2004-03-16

申请人： Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

发明人： Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0338 ,  H04L7/005

摘要： A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.

摘要翻译： 时钟和数据恢复系统（“CDR”）包括时钟发生器，用于接收输入数据的半速率相位检测器，编码器，输出恢复时钟的相位选择器，置信计数器和输出恢复数据的多路复用器。 时钟发生器以传输的串行数据的一半速率产生8相时钟信号。 相位检测器以标准采样速率的四倍采样输入数据，采用过采样数据并检测其中的相位变化，即相位超前和滞后。 编码器对相变数据进行编码。 置信计数器接收相变数据，并产生表示相变的累积净效应的信号。 相位选择器从时钟发生器接收置信计数器信号和8相时钟，并确定数据采样的最佳相位。

公开(公告)号：US20090096439A1

公开(公告)日：2009-04-16

申请号：US11870113

申请日：2007-10-10

申请人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

发明人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC分类号： G01R29/26 ,  G01R23/12

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

摘要翻译： 公开了抖动测量电路和校准抖动测量电路的方法。 抖动测量电路包括同步双相检测器和判定电路。 在测试模式中，获得由被测电路输出的时钟信号的抖动的概率分布函数（PDF）。 在校准模式中，由被测电路中的自由振荡器外部产生或产生的随机时钟用于校准同步双相检测器。 决定电路对由同步双相检测器检测的相位关系进行逻辑运算，数据锁存和计数，以获得相对于时钟信号的抖动的计数值和PDF。

公开(公告)号：US07474239B2

公开(公告)日：2009-01-06

申请号：US11774752

申请日：2007-07-09

申请人： Chau-Chin Su ,  Hung-Wen Lu ,  Shun-Min Chi

发明人： Chau-Chin Su ,  Hung-Wen Lu ,  Shun-Min Chi

IPC分类号： H03M1/06

CPC分类号： H03M1/1009 ,  H03M1/002 ,  H03M1/361

摘要： In a precisely self-calibrating high-speed analog to digital converter the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.

摘要翻译： 在精确自校准的高速模数转换器中，调节三态反相器的纵横比以微调阈值电压作为比较器。 并且由三态反相器组成的多路复用器放大来自比较器的输出的信号。 它们的三态逆变器的开关可以被适当地控制以选择最佳通道并减少不必要的功率消耗。 校准电路利用欠采样来计算比较器的占空比，选择最佳比较器和通道。 顺便说一下，本发明可以避免过程变化。

公开(公告)号：US07415089B2

公开(公告)日：2008-08-19

申请号：US10800653

申请日：2004-03-16

申请人： Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

发明人： Chau-chin Su ,  Chien-Hsi Lee ,  Hung-Wen Lu ,  Hsueh-Chin Lin ,  Yen-Pin Tseng ,  Chia-Nan Wang ,  Uan-Jiun Liu

IPC分类号： H04L7/00

CPC分类号： H04L7/0338 ,  H04L7/005

摘要： A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.

摘要翻译： 时钟和数据恢复系统（“CDR”）包括时钟发生器，用于接收输入数据的半速率相位检测器，编码器，输出恢复时钟的相位选择器，置信计数器和输出恢复数据的多路复用器。 时钟发生器以传输的串行数据的一半速率产生8相时钟信号。 相位检测器以标准采样速率的四倍采样输入数据，采用过采样数据并检测其中的相位变化，即相位超前和滞后。 编码器对相变数据进行编码。 置信计数器接收相变数据，并产生表示相变的累积净效应的信号。 相位选择器从时钟发生器接收置信计数器信号和8相时钟，并确定数据采样的最佳相位。

公开(公告)号：US20080180289A1

公开(公告)日：2008-07-31

申请号：US11774752

申请日：2007-07-09

申请人： CHAU-CHIN SU ,  HUNG-WEN LU ,  SHUN-MIN CHI

发明人： CHAU-CHIN SU ,  HUNG-WEN LU ,  SHUN-MIN CHI

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1009 ,  H03M1/002 ,  H03M1/361

摘要： A precisely self-calibrating high-speed analog to digital converter is disclosed, wherein the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.

摘要翻译： 公开了一种精确自校准的高速模数转换器，其中调节三态反相器的纵横比以微调阈值电压作为比较器。 并且由三态反相器组成的多路复用器放大来自比较器的输出的信号。 它们的三态逆变器的开关可以被适当地控制以选择最佳通道并减少不必要的功率消耗。 校准电路利用欠采样来计算比较器的占空比，选择最佳比较器和通道。 顺便说一下，本发明可以避免过程变化。

公开(公告)号：US20090072869A1

公开(公告)日：2009-03-19

申请号：US11854560

申请日：2007-09-13

申请人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

发明人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  G11C27/026

摘要： Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

摘要翻译： 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

公开(公告)号：US07495479B1

公开(公告)日：2009-02-24

申请号：US11854560

申请日：2007-09-13

申请人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

发明人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC分类号： H03K17/00

CPC分类号： G11C27/024 ,  G11C27/026

摘要： Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

摘要翻译： 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

公开(公告)号：US20080150583A1

公开(公告)日：2008-06-26

申请号：US11853003

申请日：2007-09-10

申请人： Hung Wen LU ,  Chauchin SU

发明人： Hung Wen LU ,  Chauchin SU

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018571 ,  H03K19/00323 ,  H03K19/01707 ,  H04L25/0272 ,  H04L25/028

摘要： A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

摘要翻译： 具有输入端和输出端的缓冲电路包括具有耦合到输入端的输入节点和耦合到输出端的输出节点的第一反相器，具有耦合到参考电压的输入节点的第二反相器和输出节点 具有耦合到所述输出端的输入节点和耦合到所述第二反相器的输出节点的输出节点的第三反相器，具有耦合到所述第二反相器的输出节点的输入节点的第四反相器和耦合到所述第二反相器的输出节点的输出节点 输出端子，具有输入节点和耦合到输出端子的输出节点的第五反相器，具有耦合到第二反相器的输出节点的输入节点和输出节点的第六反相器，第一电阻元件耦合在输出端 端子和第五反相器的输入节点，第二电阻元件耦合在第二反相器的输出节点和第六反相器的输入节点之间。

公开(公告)号：US07912166B2

公开(公告)日：2011-03-22

申请号：US11870113

申请日：2007-10-10

申请人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

发明人： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC分类号： H04L7/00

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

摘要翻译： 公开了抖动测量电路和校准抖动测量电路的方法。 抖动测量电路包括同步双相检测器和判定电路。 在测试模式中，获得由被测电路输出的时钟信号的抖动的概率分布函数（PDF）。 在校准模式中，由被测电路中的自由振荡器外部产生或产生的随机时钟用于校准同步双相检测器。 决定电路对由同步双相检测器检测的相位关系进行逻辑运算，数据锁存和计数，以获得相对于时钟信号的抖动的计数值和PDF。