利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.013 秒)

    Microprocessor architecture capable of supporting multiple heterogeneous processors
    2.
    发明授权
    Microprocessor architecture capable of supporting multiple heterogeneous processors 失效
    支持多种异构处理器的微处理器架构

    公开(公告)号：US06272579B1

    公开(公告)日：2001-08-07

    申请号：US09253761

    申请日：1999-02-22

    申请人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    发明人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    IPC分类号： G06F1314

    CPC分类号： G06F12/0813 ,  G06F12/0215 ,  G06F12/0831 ,  G06F12/0855 ,  G06F13/18 ,  G06F13/4022 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173

    摘要： A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption. The system also includes a tracker to keep track of the number of times each of the factors occurs and a priority changer to change the priority of the devices as a function of the intrinsic priority and the number.

    摘要翻译： 用于在能够支持多个处理器的多处理器架构中传送数据的系统和方法。 该系统包括优先级分配器，该优先级分配器根据分配给每个设备的内在优先级向输入/输出单元（IOU），D-缓存和I缓存设备请求提供动态优先级，并且包括存在一个 所请求的地址和先前服务的请求之间的行匹配，设备被拒绝服务的次数以及设备未被中断的次数。 该系统还包括跟踪器以跟踪每个因素发生的次数，以及优先级改变器，以根据内在优先级和数量来改变设备的优先级。

    System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit
    6.
    发明授权
    System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit 失效
    用于调整与寻求访问存储器阵列单元的多个设备相关联的优先级的系统和方法

    公开(公告)号：US06219763B1

    公开(公告)日：2001-04-17

    申请号：US09253760

    申请日：1999-02-22

    申请人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    发明人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    IPC分类号： G06F1202

    CPC分类号： G06F12/0813 ,  G06F12/0215 ,  G06F12/0831 ,  G06F12/0855 ,  G06F13/18 ,  G06F13/4022 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173

    摘要： A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include a latch for storing a previous row address request, and a comparator for comparing a previously latched row address request with a present row address request associated with a specific device of the multiple devices seeking access to the MAU. The comparator asserts a row match signal when the previously latched row address request matches the present row address request. The system further includes an arbiter for controlling priorities associated with the multiple devices seeking access to the MAU. The arbiter increases a priority of the specific device when the row match signal is asserted

    摘要翻译： 一种用于在包括存储器阵列单元（MAU）和寻求访问MAU的多个设备的微处理器架构中传送数据的系统。 该系统具有用于检测并指示连续行地址之间的行匹配的行匹配电路。 行匹配电路包括用于存储先前行地址请求的锁存器，以及用于将先前锁存的行地址请求与寻求访问MAU的多个设备的特定设备相关联的当前行地址请求进行比较的比较器。 当先前锁存的行地址请求与当前的行地址请求相匹配时，比较器会产生一个行匹配信号。 该系统还包括用于控制与寻求访问MAU的多个设备相关联的优先级的仲裁器。 当行匹配信号被断言时，仲裁器增加特定设备的优先级

    System and method for reducing the critical path in memory control unit and input/output control unit operations
    8.
    发明授权
    System and method for reducing the critical path in memory control unit and input/output control unit operations 失效
    用于减少存储器控制单元和输入/输出控制单元操作中的关键路径的系统和方法

    公开(公告)号：US5828861A

    公开(公告)日：1998-10-27

    申请号：US846231

    申请日：1992-03-06

    申请人： Yoshiyuki Miyayama ,  Cheng-Long Tang

    发明人： Yoshiyuki Miyayama ,  Cheng-Long Tang

    IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F13/42 ,  G06F9/00

    CPC分类号： G06F13/4243 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3867

    摘要： A system and method for eliminating the critical path of a processor-based system by sending a signal to transition memory and/or I/O control units to a READ/WRITE state prior to the end of the complete instruction decode. If the decoding phase of the opcode of the instruction reveals that a read-write step is to be carried out wherein memory or an I/O device must be accessed, the processor immediately sends a read-write request to the memory control unit and the I/O control unit prior to decoding the balance of the instruction. Once the balance of the instruction has been decoded and the access location is determined to be in either memory or an I/O device, a cancellation process takes place. In this cancellation process, if the access location is in memory, the I/O unit transitions from the read-write state to an idle state. If, however, the access destination is determined to be an I/O device, the memory control unit transitions from the read-write state to the idle state.

    摘要翻译： 一种用于通过在完成指令解码结束之前将转换存储器和/或I / O控制单元发送到READ / WRITE状态的信号来消除基于处理器的系统的关键路径的系统和方法。 如果指令的操作码的解码阶段显示要进行读写步骤，其中必须存储存储器或I / O设备，则处理器立即向存储器控制单元发送读写请求，并且 I / O控制单元在解码指令的平衡之前。 一旦指令的平衡被解码并且确定访问位置在存储器或I / O设备中，则进行取消处理。 在该取消处理中，如果访问位置在存储器中，I / O单元从读写状态转换到空闲状态。 然而，如果将访问目的地确定为I / O设备，则存储器控制单元从读写状态转换到空闲状态。

    Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption
    9.
    发明授权
    Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption 失效
    具有基于先前服务地址的行匹配的动态优先级的多处理器系统，拒绝服务的次数和不间断地服务的次数

    公开(公告)号：US5754800A

    公开(公告)日：1998-05-19

    申请号：US442649

    申请日：1995-05-16

    申请人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    发明人： Derek J. Lentz ,  Yasuaki Hagiwara ,  Te-Li Lau ,  Cheng-Long Tang ,  Le Trong Nguyen

    IPC分类号： G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F13/18 ,  G06F13/362 ,  G06F13/40 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173 ,  G06F15/177 ,  G06F13/14

    CPC分类号： G06F12/0813 ,  G06F12/0855 ,  G06F13/18 ,  G06F13/4022 ,  G06F15/167 ,  G06F15/17 ,  G06F15/173 ,  G06F12/0215 ,  G06F12/0831

    摘要： A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network and interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing the priority of the devices based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

    摘要翻译： 一种包括能够支持多个处理器的多处理器架构的计算机系统，包括存储器阵列单元（MAU），包括数据，地址和控制信号总线的MAU系统总线，包括数据，地址和控制信号总线的I / O总线，多个 的I / O设备和多个微处理器。 数据和指令高速缓存和I / O设备之间的数据传输以及存储器和其他I / O设备使用交换机网络和接口电路进行处理。 存储器总线的访问由使用固定和动态优先级方案的仲裁电路控制。 提供了一种行匹配比较电路，用于通过对具有相同行地址的存储器位置的连续请求提供更高的优先级来减少存储器等待时间。 通过基于设备的内在优先级，基于行匹配的服务请求次数，设备被拒绝服务的次数来改变设备的优先级来提供动态切换/端口仲裁 ，以及设备已被维护的次数。