公开(公告)号：US6008106A

公开(公告)日：1999-12-28

申请号：US915693

申请日：1997-08-21

申请人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

发明人： Tuby Tu ,  Chen Kuang-Chao ,  Cheng-Tsung Ni ,  Chih-Hsun Chu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/7621

摘要： A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

摘要翻译： 描述了通过使用粗略氧化物掩膜形成集成电路的隔离区域的方法。 首先，在硅衬底的表面上形成第一电介质层。 然后将第一介电层图案化以限定有源器件区域和隔离区域。 接下来，在硅衬底表面上形成非常薄的二氧化硅层，随后沉积具有覆盖二氧化硅层的适当晶粒尺寸的粗大氧化物层。 通过使用粗糙氧化物晶粒作为蚀刻掩模，自发蚀刻下面的二氧化硅层和硅衬底，以在隔离区域中形成多个沟槽。 接下来，剥离粗糙的氧化物颗粒和二氧化硅层。 然后进行归档氧化以完成场氧化物隔离层。

公开(公告)号：US5811344A

公开(公告)日：1998-09-22

申请号：US789495

申请日：1997-01-27

申请人： Tuby Tu ,  Kuang-Chao Chen ,  May Wang

发明人： Tuby Tu ,  Kuang-Chao Chen ,  May Wang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/72

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86

摘要： The present invention relates to a stacked capacitor of a DRAM cell, particully remarkably increasing a surface area of a storage electrode of a stacked capacitor without increasing an occupation area and a complexity of fabrication thereof. According to the invention, by use of depositing a protection polysilicon layer on a rugged polysilicon layer, which can provide an increased surface area of a storage electrode, a chemical oxide layer underlying the rugged polysilicon layer is protected by the protection polysilicon layer during a HF dip and thus a peeling of the rugged polysilicon layer as a result of the chemical oxide loss will not occur, thereby preventing a production yield loss.

摘要翻译： 本发明涉及一种DRAM单元的叠层电容器，其特征在于显着地增加了层叠电容器的存储电极的表面积，而不增加占用面积及其制造的复杂性。 根据本发明，通过在保持多晶硅层上沉积保护多晶硅层，其可以提供存储电极的增加的表面积，在耐久性多晶硅层下面的化学氧化物层在HF期间被保护多晶硅层保护 因此不会发生由于化学氧化物损失导致的粗糙多晶硅层的剥离，从而防止了生产成品率的损失。

公开(公告)号：US6037251A

公开(公告)日：2000-03-14

申请号：US3153

申请日：1998-01-06

申请人： Tuby Tu ,  Chin-Ta Wu ,  Chen Kuang-Chao ,  Dinos Huang

发明人： Tuby Tu ,  Chin-Ta Wu ,  Chen Kuang-Chao ,  Dinos Huang

IPC分类号： H01L21/027 ,  H01L21/3105 ,  H01L21/4763

CPC分类号： H01L21/0276 ,  H01L21/31055

摘要： A process for intermetal SOG/SOP dielectric planarization without having effect is described. First, a silicon-rich oxide (SRO) layer is formed on a substrate surface. Next, a metal layer and an antireflective coating (ARC) layer are sequentially deposited over the SRO layer. The metal layer and ARC layer are then etched to define metal patterns by the conventional lithography and etching techniques. Next, an Ozone-TEOS (O.sub.3 -TEOS) layer and a SOG layer are then formed over the entire substrate surface. Next, the O.sub.3 -TEOS layer and SOG layer are subjected to etching back treatment to obtain a planar substrate surface which only has a small portion of the O.sub.3 -TEOS layer covered on the substrate surface. The etching back treatment can be PEB, TEB or CMP techniques. Finally, a passivation layer is deposited over the remaining of O.sub.3 -TEOS layer.

摘要翻译： 描述了不具有影响的金属间SOG / SOP电介质平坦化的工艺。 首先，在基板表面上形成富硅氧化物（SRO）层。 接下来，顺序地在SRO层上沉积金属层和抗反射涂层（ARC）层。 然后通过常规的光刻和蚀刻技术蚀刻金属层和ARC层以限定金属图案。 接着，在整个基板表面上形成臭氧-TEOS（O3-TEOS）层和SOG层。 接着，对O3-TEOS层和SOG层进行回蚀处理，得到在基板表面仅覆盖有少部分O3-TEOS层的平面基板表面。 蚀刻后处理可以是PEB，TEB或CMP技术。 最后，钝化层沉积在剩余的O3-TEOS层上。

公开(公告)号：US6001745A

公开(公告)日：1999-12-14

申请号：US59366

申请日：1998-04-14

申请人： Tuby Tu ,  Danny Wu ,  Kuang-Chao Chen

发明人： Tuby Tu ,  Danny Wu ,  Kuang-Chao Chen

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/316

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76825 ,  H01L21/76831 ,  H01L2924/0002

摘要： The present invention relates to a method for forming a VIA in an Inter Metal Dielectric (IMD) containing Spin On Glass (SOG). The IMD is formed by 1) depositing a first silicon dioxide layer through a Chemical Vapor Deposition (CVD) process; 2) depositing a Spin On Glass (SOG) layer; and 3) depositing a second silicon dioxide layer through a Chemical Vapor Deposition process. Afterward, before the VIA is formed by an Inter Metal Dielectric (IMD) etching process, a selective ion implantation process is performed to densify the Spin On Glass(SOG) layer. By this arrangement, the outgassing effect of the Spin On Glass (SOG) during a subsequent metal deposition process can be therefore prevented.

摘要翻译： 本发明涉及一种在包含旋转玻璃（SOG）的金属介质（IMD）中形成VIA的方法。 IMD通过以下方式形成：1）通过化学气相沉积（CVD）工艺沉积第一二氧化硅层; 2）沉积旋涂玻璃（SOG）层; 和3）通过化学气相沉积工艺沉积第二个二氧化硅层。 之后，在通过金属间介电（IMD）蚀刻工艺形成VIA之前，进行选择性离子注入工艺以使玻璃旋转（SOG）层致密化。 通过这种布置，可以防止随后的金属沉积过程中旋转玻璃（SOG）的除气效果。

公开(公告)号：US5851867A

公开(公告)日：1998-12-22

申请号：US697623

申请日：1996-08-27

申请人： Kuang-Chao Chen ,  Tuby Tu

发明人： Kuang-Chao Chen ,  Tuby Tu

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L31/0236 ,  H01L21/8234 ,  H01L21/31

CPC分类号： H01L28/84 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L31/0236 ,  Y02E10/50

摘要： The present invention relates to a rugged stacked oxide layer structure which remarkably increases an area of a subsequent deposition layer over the rugged stacked oxide layer. The enlargement of the area of a deposition layer over the rugged oxide layer enables one to ameliorate an electrical characteristic of a device and provide a higher integration density. For example, the rugged stacked oxide layer can be used to provide a higher capacitance by enlarging the area of a storage electrode of a capacitor. Similarly it can also be used to increase light absorption of a photodetector per unit area by enlarging an interfacial area of a P-N junction of the photodetector.

摘要翻译： 本发明涉及一种坚固的层叠氧化物层结构，其显着地增加了凹凸层叠氧化物层上的后续沉积层的面积。 在粗糙氧化物层上扩大沉积层的面积使得能够改善器件的电特性并提供更高的集成密度。 例如，通过放大电容器的存储电极的面积，可以使用坚固的层叠氧化物层来提供更高的电容。 类似地，也可以通过扩大光电检测器的P-N结的界面面积来增加每单位面积的光检测器的光吸收。

公开(公告)号：US5989971A

公开(公告)日：1999-11-23

申请号：US926036

申请日：1997-09-09

申请人： Tuby Tu ,  Kuang-Chao Chen

发明人： Tuby Tu ,  Kuang-Chao Chen

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/1085 ,  H01L28/82 ,  Y10S438/947 ,  Y10S438/964

摘要： A method for forming a trenched polysilicon structure can be applied to a semiconductor device. The method includes steps of: a) providing a polysilicon layer; b) forming a dielectric layer on the polysilicon layer; c) forming a rugged oxide layer on the dielectric layer; d) removing a portion of the dielectric layer which is not covered by the rugged oxide layer for exposing a corresponding portion of the polysilicon layer; e) forming a plurality of microtrenches by etching the corresponding portion of the polysilicon layer; and f) removing the rugged oxide layer and the dielectric layer to obtain the trenched polysilicon structure.

摘要翻译： 用于形成沟槽多晶硅结构的方法可以应用于半导体器件。 该方法包括以下步骤：a）提供多晶硅层; b）在所述多晶硅层上形成介电层; c）在介电层上形成粗糙的氧化物层; d）去除不被粗糙氧化物层覆盖的介电层的一部分，以暴露多晶硅层的相应部分; e）通过蚀刻多晶硅层的相应部分形成多个微通孔; 以及f）去除粗糙的氧化物层和电介质层以获得沟槽的多晶硅结构。

公开(公告)号：US5869399A

公开(公告)日：1999-02-09

申请号：US908319

申请日：1997-08-07

申请人： Tuby Tu ,  Kuang-Chao Chen

发明人： Tuby Tu ,  Kuang-Chao Chen

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L28/82

摘要： The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.

摘要翻译： 本发明涉及一种用于增加半导体器件中的凹凸多晶硅层的可利用表面积的方法。 本方法包括以下步骤：（a）提供由多晶硅组成的预生长的耐久多晶硅层，其中掺杂有第一掺杂剂; （b）在预生长的粗糙多晶硅层上形成另一个多晶硅层; （c）通过各向异性蚀刻工艺去除另一多晶硅层的一部分以暴露预生长的耐磨多晶硅层的上表面; 和（d）蚀刻所得的预生长的粗糙多晶硅层，其中预生长的耐久多晶硅层与另一多晶硅层的蚀刻选择比大于1，以获得具有增加的可用表面积的粗糙多晶硅层。 包含根据本发明制造的坚固多晶硅层的半导体器件可以在相对致密和小的半导体芯片中很好地工作。

公开(公告)号：US5869394A

公开(公告)日：1999-02-09

申请号：US741195

申请日：1996-10-29

申请人： Kuang-Chao Chen ,  Tuby Tu

发明人： Kuang-Chao Chen ,  Tuby Tu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76829

摘要： A method for forming a planarization layer on a semiconductor device including the steps of first providing a substrate, then depositing a layer of a silicon-rich oxide material, then forming metal interconnects on the silicon-rich oxide layer, and depositing a TEOS-ozone oxide layer over the metal interconnects and the silicon-rich oxide layer such that a substantially planar surface is obtained.

摘要翻译： 一种在半导体器件上形成平坦化层的方法，包括以下步骤：首先提供衬底，然后沉积富硅氧化物材料层，然后在富硅氧化物层上形成金属互连，并沉积TEOS-臭氧 金属互连上的氧化物层和富硅氧化物层，使得获得基本平坦的表面。

公开(公告)号：US5960279A

公开(公告)日：1999-09-28

申请号：US697622

申请日：1996-08-27

申请人： Kuang-Chao Chen ,  Tuby Tu

发明人： Kuang-Chao Chen ,  Tuby Tu

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/84

摘要： The present invention relates to a stacked memory capacitor of a DRAM cell, particularly, relates to a DRAM cell having a memory capacitor whose storage electrode possesses a remarkably increase area without increasing its occupation area and the complexity of fabrication thereof. By disposing the storage electrode of the memory capacitor on a rugged stacked oxide layer, the area of the storage electrode is remarkably enlarged since the growing of the storage electrode made of a doped polysilicon layer is followed along the topography of the rugged stacked oxide layer, thereby, resulting in a rugged surface thereof. The entire rugged surface of the storage electrode is covered with a dielectric layer to form a plate electrode made of a doped polysilicon layer. The memory capacitor provided by the invention achieves a higher capacitance while maintaining the same occupation area and packing density as that of the conventional arts.

摘要翻译： 本发明涉及一种DRAM单元的堆叠式存储电容器，特别涉及一种具有存储电容器的存储电容器的DRAM单元，其存储电极具有显着增加的面积而不增加其占用面积及其制造的复杂性。 通过将存储电容器的存储电极设置在坚固的堆叠氧化物层上，由于沿着凹凸的堆叠氧化物层的形貌遵循由掺杂多晶硅层制成的存储电极的生长，所以存储电极的面积显着增大， 从而导致其表面粗糙。 存储电极的整个粗糙表面被电介质层覆盖以形成由掺杂多晶硅层制成的平板电极。 本发明提供的存储电容器在保持与传统技术相同的占用面积和封装密度的同时实现更高的电容。

公开(公告)号：US5883015A

公开(公告)日：1999-03-16

申请号：US887886

申请日：1997-07-03

申请人： Kent Liao ,  Dinos Huang ,  Tuby Tu ,  Kuang-Chao Chen ,  Wen-Doe Su

发明人： Kent Liao ,  Dinos Huang ,  Tuby Tu ,  Kuang-Chao Chen ,  Wen-Doe Su

IPC分类号： C23C16/40 ,  H01L21/314 ,  H01L21/316

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

摘要： The method for depositing a dielectric layer can be used to evenly deposit the dielectric layer to be applied to a semiconductor device. The method includes steps of: a) providing a substrate; b) depositing a first dielectric film on the subtrate; c) introducing an oxygen plasma for eliminating an uneven distribution of charges on a surface of the substrate; and d) forming a second dielectric film on the first dielectric film treated with the oxygen plasma for obtaining the dielectric layer having a uniform thickness on the substrate,

摘要翻译： 用于沉积电介质层的方法可用于均匀地沉积要施加到半导体器件的介质层。 该方法包括以下步骤：a）提供衬底; b）在所述缓冲液上沉积第一介电膜; c）引入氧等离子体以消除基板表面上电荷的不均匀分布; 以及d）在用氧等离子体处理的第一电介质膜上形成第二电介质膜，以获得在衬底上具有均匀厚度的电介质层，