公开(公告)号：US08755809B2

公开(公告)日：2014-06-17

申请号：US13169209

申请日：2011-06-27

Applicant: Tae Soo Kwon ,  Woo Geun Ahn ,  Dong Ho Cho ,  Ju Yong Lee ,  Jong Bu Lim ,  Hyun Gi Ahn

Inventor： Tae Soo Kwon ,  Woo Geun Ahn ,  Dong Ho Cho ,  Ju Yong Lee ,  Jong Bu Lim ,  Hyun Gi Ahn

IPC: H04W72/00

CPC classification number: H04W72/048 ,  H04W64/006

Abstract: Provided is a communication method of a base station and a target terminal. Resources used for a channel feedback may be reduced by determining a wireless resource based on information about a channel and information about a mobility of the target terminal in each of at least one route, and by feeding back channel state information.

Abstract translation: 提供了基站和目标终端的通信方法。 可以通过基于关于信道的信息和关于目标终端在至少一个路由中的每一个中的移动性的信息以及通过反馈信道状态信息来确定无线资源来减少用于信道反馈的资源。

公开(公告)号：US20120217648A1

公开(公告)日：2012-08-30

申请号：US13298422

申请日：2011-11-17

Applicant: Jae Hyoung Park ,  Seung Ki Lee ,  Ju Yong Lee

Inventor： Jae Hyoung Park ,  Seung Ki Lee ,  Ju Yong Lee

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768

CPC classification number: B81C1/00301 ,  B81B2207/096 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate structure, an electronic device package using the same, and methods for manufacturing the same are disclosed. First, a via hole pattern is formed by etching an upper surface of a first substrate. A pattern layer of a second substrate is formed on the first substrate by filling the via hole pattern with a material for the second substrate by reflow. A via hole pattern is formed in the pattern layer of the second substrate by patterning the upper surface of the first substrate. Moreover, a via plug filling the via hole pattern is formed by a plating process, for example, thereby forming a through substrate structure, which can be used in an electronic device package.

Abstract translation: 公开了一种贯穿基板结构，使用其的电子器件封装及其制造方法。 首先，通过蚀刻第一基板的上表面形成通孔图案。 通过回流填充用于第二基板的材料的通孔图案，在第一基板上形成第二基板的图案层。 通过图案化第一基板的上表面，在第二基板的图案层中形成通孔图案。 此外，通过电镀工艺形成填充通孔图案的通孔塞，从而形成可用于电子器件封装的通孔基板结构。

公开(公告)号：US20080266927A1

公开(公告)日：2008-10-30

申请号：US12055035

申请日：2008-03-25

Applicant: Ju-Yong LEE ,  Sung-Ho JANG ,  Tae-Young CHUNG ,  Joon HAN

Inventor： Ju-Yong LEE ,  Sung-Ho JANG ,  Tae-Young CHUNG ,  Joon HAN

IPC: G11C5/06 ,  H01L21/768

CPC classification number: H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract translation: 提供了具有6F 2 2布局的半导体集成电路器件。 半导体集成电路器件包括衬底; 设置在所述基板中并沿第一方向延伸的多个单位活性区域; 第一和第二存取晶体管，包括设置在衬底上的第一和第二栅极线，并且沿与第一方向成锐角的第二方向延伸跨过单元有源区; 设置在第一和第二栅极线之间的衬底中的第一接合区域和设置在不设置第一接合区域的第一和第二栅极线的侧面上的第二接合区域; 多个位线设置在所述基板上并沿与所述第一方向成锐角的第三方向延伸; 以及直接连接第一连接区域和位线的多个位线触点。

公开(公告)号：US20080198797A1

公开(公告)日：2008-08-21

申请号：US12034689

申请日：2008-02-21

Applicant: Eun-Chan Park ,  Ki-Back Kim ,  Ju-Yong Lee

Inventor： Eun-Chan Park ,  Ki-Back Kim ,  Ju-Yong Lee

IPC: H04Q7/00

CPC classification number: H04W72/005

Abstract: Disclosed is an apparatus and method for an MBS service in a BWA system. An apparatus of a base station includes a time controller, a CAC processor, and a buffer controller. The time controller manages a broadcast start time and a broadcast end time and generates a broadcast start message at a predetermined time before the actual broadcast start time. Upon receipt of the generated broadcast start message from the time controller, the CAC processor calculates a capacity decrease due to broadcast service and subtracts the capacity decrease from the current available capacity to update the available capacity. Upon receipt of the generated broadcast start message from the time controller, the buffer controller controls the buffer occupation of unicast traffic in order to provide the buffer space required for a broadcast service.

Abstract translation: 公开了一种BWA系统中的MBS服务的装置和方法。 基站的装置包括时间控制器，CAC处理器和缓冲器控制器。 时间控制器管理广播开始时间和广播结束时间，并且在实际广播开始时间之前的预定时间生成广播开始消息。 当从时间控制器接收到生成的广播开始消息时，CAC处理器计算由广播服务引起的容量减少，并从当前可用容量减去容量减少以更新可用容量。 当从时间控制器接收到生成的广播开始消息时，缓冲器控制器控制单播业务的缓冲器占用，以提供广播服务所需的缓冲区空间。

公开(公告)号：US20070004129A1

公开(公告)日：2007-01-04

申请号：US11427734

申请日：2006-06-29

Applicant: Ju-Yong LEE ,  Tae-Young CHUNG ,  Kyu-Hyun LEE ,  Yong-Sung KIM

Inventor： Ju-Yong LEE ,  Tae-Young CHUNG ,  Kyu-Hyun LEE ,  Yong-Sung KIM

IPC: H01L21/8242 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/66795

Abstract: In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside the trench and covering a sidewall of the active region inside the trench. A separation layer is formed between two neighboring word lines to separate the two neighboring word lines of the plurality of word lines inside the trench with a predetermined distance. The separation layer comprises a second insulating material having an etch selectivity with respect to the first insulating material.

Abstract translation: 在一个实施例中，半导体器件包括由形成在具有预定深度的衬底中的沟槽限定的多个鳍状有源区域; 形成在所述沟槽内并包括第一绝缘材料的隔离层; 以及形成在沟槽内的隔离层上并覆盖沟槽内的有源区的侧壁的多个字线。 在两个相邻字线之间形成分离层，以将沟槽内的多个字线的两个相邻字线以预定距离分开。 分离层包括具有相对于第一绝缘材料的蚀刻选择性的第二绝缘材料。

公开(公告)号：US20060261392A1

公开(公告)日：2006-11-23

申请号：US11458353

申请日：2006-07-18

Applicant: Ju-Yong LEE ,  Kyu-Hyun LEE

Inventor： Ju-Yong LEE ,  Kyu-Hyun LEE

IPC: H01L29/94

CPC classification number: H01L27/10855 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract translation: 本文公开了一种半导体器件及其制造方法，其随着尺寸设计限制的降低而增加这些器件的可靠性。 通常，在基板上形成包括导电膜图案和第二绝缘膜图案的第一绝缘膜和布线。 在布线的侧壁上形成包括基于氧化硅的材料的第三绝缘膜图案，并且在布线上形成用于限定接触孔区域的侧壁上的接触图形和间隔物。 接触孔接触第三绝缘膜图案的表面并穿过第一绝缘膜。 因此，可以使布线中使用的第二绝缘膜图案的厚度最小化，从而增加布线之间的间隙填充余量。 由于在布线的侧壁上形成具有低介电常数的氧化硅间隔物，所以布线之间的寄生电容可以减小。

公开(公告)号：US07920400B2

公开(公告)日：2011-04-05

申请号：US12055035

申请日：2008-03-25

Applicant: Ju-Yong Lee ,  Sung-Ho Jang ,  Tae-Young Chung ,  Joon Han

Inventor： Ju-Yong Lee ,  Sung-Ho Jang ,  Tae-Young Chung ,  Joon Han

IPC: G11C5/06

CPC classification number: H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621

Abstract: A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.

Abstract translation: 提供具有6F2布局的半导体集成电路器件。 半导体集成电路器件包括衬底; 设置在所述基板中并沿第一方向延伸的多个单位活性区域; 第一和第二存取晶体管，包括设置在衬底上的第一和第二栅极线，并且沿与第一方向成锐角的第二方向延伸跨过单元有源区; 设置在第一和第二栅极线之间的衬底中的第一接合区域和设置在不设置第一接合区域的第一和第二栅极线的侧面上的第二接合区域; 多个位线设置在所述基板上并沿与所述第一方向成锐角的第三方向延伸; 以及直接连接第一连接区域和位线的多个位线触点。

公开(公告)号：US07180118B2

公开(公告)日：2007-02-20

申请号：US10830895

申请日：2004-04-22

Applicant: Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

Inventor： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC: H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

Abstract: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

Abstract translation: 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US08569164B2

公开(公告)日：2013-10-29

申请号：US13298422

申请日：2011-11-17

Applicant: Jae Hyoung Park ,  Seung Ki Lee ,  Ju Yong Lee

Inventor： Jae Hyoung Park ,  Seung Ki Lee ,  Ju Yong Lee

IPC: H01L21/4763

CPC classification number: B81C1/00301 ,  B81B2207/096 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate structure, an electronic device package using the same, and methods for manufacturing the same are disclosed. First, a via hole pattern is formed by etching an upper surface of a first substrate. A pattern layer of a second substrate is formed on the first substrate by filling the via hole pattern with a material for the second substrate by reflow. A via hole pattern is formed in the pattern layer of the second substrate by patterning the upper surface of the first substrate. Moreover, a via plug filling the via hole pattern is formed by a plating process, for example, thereby forming a through substrate structure, which can be used in an electronic device package.

Abstract translation: 公开了一种贯穿基板结构，使用其的电子器件封装及其制造方法。 首先，通过蚀刻第一基板的上表面形成通孔图案。 通过回流填充用于第二基板的材料的通孔图案，在第一基板上形成第二基板的图案层。 通过图案化第一基板的上表面，在第二基板的图案层中形成通孔图案。 此外，通过电镀工艺形成填充通孔图案的通孔塞，从而形成可用于电子器件封装的通孔基板结构。

公开(公告)号：US08411563B2

公开(公告)日：2013-04-02

申请号：US12034689

申请日：2008-02-21

Applicant: Eun-Chan Park ,  Ki-Back Kim ,  Ju-Yong Lee

Inventor： Eun-Chan Park ,  Ki-Back Kim ,  Ju-Yong Lee

IPC: H04L1/00

CPC classification number: H04W72/005

Abstract: Disclosed is an apparatus and method for an MBS service in a BWA system. An apparatus of a base station includes a time controller, a CAC processor, and a buffer controller. The time controller manages a broadcast start time and a broadcast end time and generates a broadcast start message at a predetermined time before the actual broadcast start time. Upon receipt of the generated broadcast start message from the time controller, the CAC processor calculates a capacity decrease due to broadcast service and subtracts the capacity decrease from the current available capacity to update the available capacity. Upon receipt of the generated broadcast start message from the time controller, the buffer controller controls the buffer occupation of unicast traffic in order to provide the buffer space required for a broadcast service.

Abstract translation: 公开了一种BWA系统中的MBS服务的装置和方法。 基站的装置包括时间控制器，CAC处理器和缓冲器控制器。 时间控制器管理广播开始时间和广播结束时间，并且在实际广播开始时间之前的预定时间生成广播开始消息。 当从时间控制器接收到生成的广播开始消息时，CAC处理器计算由广播服务引起的容量减少，并从当前可用容量减去容量减少以更新可用容量。 当从时间控制器接收到生成的广播开始消息时，缓冲器控制器控制单播业务的缓冲器占用，以提供广播服务所需的缓冲区空间。