公开(公告)号：US5865900A

公开(公告)日：1999-02-02

申请号：US725805

申请日：1996-10-04

申请人： Chiarn-Lung Lee ,  Huai-Jen Shu ,  Ying-Tzu Yen

发明人： Chiarn-Lung Lee ,  Huai-Jen Shu ,  Ying-Tzu Yen

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/3065 ,  C23G1/02 ,  H01L21/306

CPC分类号： H01L21/02071 ,  Y10S438/906

摘要： A method for removing a metal-fluoropolymer residue from an integrated circuit structure within an integrated circuit. There is first provided an integrated circuit having formed therein a metal-fluoropolymer residue. The metal-fluoropolymer residue is formed from a first plasma etch method employing a fluorocarbon containing etchant gas composition within the presence of a conductor metal layer within the integrated circuit. The metal-fluoropolymer residue is then exposed to a second plasma etch method employing a chlorine containing etchant gas composition to form from the metal-fluoropolymer residue a chlorine containing plasma treated metal-fluoropolymer residue. Finally, the chlorine containing plasma treated metal-fluoropolymer residue is removed from the integrated circuit through a stripping method sequentially employing an aqueous acid solution followed by an organic solvent.

摘要翻译： 一种从集成电路内的集成电路结构去除金属 - 含氟聚合物残留物的方法。 首先提供了在其中形成有金属 - 含氟聚合物残留物的集成电路。 金属 - 含氟聚合物残留物是通过在集成电路内的导体金属层存在下使用含有碳氟化合物的蚀刻剂气体组成的第一等离子体蚀刻方法形成的。 然后将金属 - 含氟聚合物残余物暴露于使用含氯蚀刻剂气体组合物的第二等离子体蚀刻方法，从金属 - 含氟聚合物残余物形成含氯等离子体处理的金属 - 含氟聚合物残余物。 最后，通过依次使用酸水溶液和有机溶剂的汽提方法从集成电路中除去含氯等离子体处理的金属 - 氟聚合物残余物。

公开(公告)号：US06245688B1

公开(公告)日：2001-06-12

申请号：US09320762

申请日：1999-05-27

申请人： Yuan-Shing Jing ,  Han-Chung Chen ,  Chiarn-Lung Lee

发明人： Yuan-Shing Jing ,  Han-Chung Chen ,  Chiarn-Lung Lee

IPC分类号： H01L21311

CPC分类号： H01L21/02129 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/3105 ,  H01L21/31625

摘要： A method to store wafers, immediately after the deposition of a layer of BPSG, into an environment of dry air or dry N2 or dry Ar or a N2O plasma chamber. This storage can occur over a variable period of time and with a variable delay between BPSG deposition and BPSG flow, dependent on which storage environment is applied. The surface of the deposited layer of BPSG is, in doing so, not exposed to H2O and the formation of unstable irregularities on the surface of the deposited BPSG is prevented.

摘要翻译： 在沉积BPSG层之后立即将晶片存储到干燥空气或干燥的N 2或干燥的Ar或N 2 O等离子体室的环境中的方法。 这种存储可以在可变时间段内发生，并且在BPSG沉积和BPSG流动之间具有可变的延迟，这取决于应用哪种存储环境。 BPSG的沉积层的表面在这样做时不暴露于H 2 O，并且防止在沉积的BPSG的表面上形成不稳定的不规则。

公开(公告)号：US6090675A

公开(公告)日：2000-07-18

申请号：US285533

申请日：1999-04-02

申请人： Chiarn-Lung Lee ,  Han-Chung Chen ,  Je Wang

发明人： Chiarn-Lung Lee ,  Han-Chung Chen ,  Je Wang

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/336

CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L29/66575

摘要： A method for forming upon a microelectronics layer upon a substrate employed within a microelectronics fabrication a silicon oxide dielectric layer with enhanced density and reduced mobile species, ionic concentration and ionic mobility. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a blanket undoped silicon oxide glass dielectric layer employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) from tetra-ethyl-ortho-silicate (TEOS) vapor, wherein a high flow rate ratio of ozone gas to TEOS vapor affords enhanced density and reduced mobile species, ionic concentration and ionic mobility in the blanket silicon oxide glass dielectric layer. There is then formed a blanket boron-phosphorus doped silicon containing glass dielectric layer over the substrate employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) to complete the dielectric layer. The blanket undoped silicon oxide glass dielectric layer serves as a barrier to diffusion of mobile species from the doped silicon containing glass dielectric layer or other dielectric layers to attenuate hot carrier injection effects, which reduces degradation of device reliability.

摘要翻译： 在微电子学制造中使用的衬底上的微电子层上形成的方法，其具有增强的密度和减少的移动物质，离子浓度和离子迁移率的氧化硅介电层。 提供了在微电子制造中使用的衬底。 在基板上形成由四乙基原硅酸盐（TEOS）蒸气采用臭氧辅助的接近大气压热化学气相沉积（APCVD）的毯状未掺杂的氧化硅玻璃介电层，其中臭氧气体与 TEOS蒸气在覆盖氧化硅玻璃介电层中提供增强的密度和降低的移动物质，离子浓度和离子迁移率。 然后，使用臭氧辅助的近大气压热化学气相沉积（APCVD）在衬底上形成覆盖硼磷掺杂的含硅玻璃介电层以完成电介质层。 覆盖未掺杂的氧化硅玻璃介电层用作阻挡来自掺杂的含硅玻璃介电层或其它电介质层的移动物质的扩散，以衰减热载流子注入效应，这降低了器件可靠性的劣化。

公开(公告)号：US5935876A

公开(公告)日：1999-08-10

申请号：US872655

申请日：1997-06-10

申请人： Chiarn-Lung Lee ,  Wei-Kun Yeh ,  Shyh-Jen Guo

发明人： Chiarn-Lung Lee ,  Wei-Kun Yeh ,  Shyh-Jen Guo

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/02164 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/76804 ,  H01L21/316

摘要： A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.

摘要翻译： 公开了一种通过使用复合电介质层形成具有通孔的半导体器件的方法。 该方法包括在设置在基底上的第一导电层上形成第一介电层，其中第一介电层具有第一蚀刻速率。 然后在第一介电层上形成第二电介质层，其中第二介电层具有高于第一蚀刻速率的第二蚀刻速率。 通过掩模和蚀刻各向同性地去除第二介电层，以使用第一介电层作为蚀刻停止层在第二介电层中形成圆形轮廓凹槽。 通过掩模和蚀刻各向异性地去除第一介电层，以在第一电介质层中形成通孔，其中圆形轮廓凹槽的底部与通孔对准。

公开(公告)号：US06440859B1

公开(公告)日：2002-08-27

申请号：US09160964

申请日：1998-09-25

申请人： Jun-Kai Peng ,  Wei-Kun Yeh ,  Chiarn-Lung Lee

发明人： Jun-Kai Peng ,  Wei-Kun Yeh ,  Chiarn-Lung Lee

IPC分类号： H01L21311

CPC分类号： H01L21/304

摘要： In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

摘要翻译： 在用于蚀刻半导体晶片的最上层的沟槽的改进方法中，执行常规的各向异性蚀刻以实现窄沟槽，并且执行各向同性蚀刻以加宽器件表面处的沟槽，并且由此围绕边缘，其中壁 的凹槽相遇晶片的表面。 在将保护带施加到晶片的器件侧以在保护晶片的背面的步骤期间的后续步骤中，槽的圆形边缘不太可能穿过带的粘合剂层，从而导致 当胶带移除时，粘合剂颗粒保留在晶片表面上。

公开(公告)号：US06294483B1

公开(公告)日：2001-09-25

申请号：US09567418

申请日：2000-05-09

申请人： Je Wang ,  Han-Chung Chen ,  Chiarn-Lung Lee

发明人： Je Wang ,  Han-Chung Chen ,  Chiarn-Lung Lee

IPC分类号： H01L2131

CPC分类号： H01L21/02129 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31625

摘要： A method for forming BPSG layers over PECVD silicon oxide layers by atmospheric chemical vapor deposition using ozone and TEOS is described. The method prevents the formation of voids in deep depressions such as are found between metallization lines or closely spaced polysilicon structures in flash memory integrated circuits. The method deposits the BPSG layer at ozone/TEOS flow rate ratio of 12:1 or greater. The voids are caused by excessive shrinkage of the BPSG which produces high stresses in the depressions during planarization reflow causing the BPSG to become detached from the underlying silicon oxide. The voids are measured as line defects in a double polysilicon flash memory circuit. The high ozone/TEOS ratio increases the density of the as-deposited BPSG layer which in turn produces reduced shrinkage of the layer during the subsequent planarization reflow. A correlation is found between BPSG shrinkage and line yield.

摘要翻译： 描述了通过使用臭氧和TEOS的大气化学气相沉积在PECVD氧化硅层上形成BPSG层的方法。 该方法防止在深层凹陷中形成空隙，例如在闪存集成电路中的金属化线或紧密间隔的多晶硅结构之间。 该方法以12：1或更高的臭氧/ TEOS流速比沉积BPSG层。 空隙由BPSG的过度收缩引起，其在平坦化回流期间在凹陷中产生高应力，导致BPSG从底层氧化硅脱离。 空隙在双晶硅闪存电路中被测量为线路缺陷。 高臭氧/ TEOS比率增加了沉积的BPSG层的密度，其又在随后的平坦化回流期间产生层的减小的收缩。 BPSG收缩率与线产量之间存在相关性。