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公开(公告)号:US20080057711A1
公开(公告)日:2008-03-06
申请号:US11511698
申请日:2006-08-29
申请人: Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人: Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号: H01L21/44
CPC分类号: H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译: 制造半导体器件,同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模,并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理,其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料,并执行平面化处理以去除多余的填充材料。
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公开(公告)号:US07727885B2
公开(公告)日:2010-06-01
申请号:US11511698
申请日:2006-08-29
申请人: Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人: Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号: H01L21/44
CPC分类号: H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译: 制造半导体器件,同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模,并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理,其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料,并执行平面化处理以去除多余的填充材料。
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公开(公告)号:US06624066B2
公开(公告)日:2003-09-23
申请号:US09783157
申请日:2001-02-14
申请人: Jiong-Ping Lu , Ching-Te Lin
发明人: Jiong-Ping Lu , Ching-Te Lin
IPC分类号: H01L214763
CPC分类号: H01L23/53238 , H01L21/76807 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要: Two barrier layers are used for a via or contact. A thin CVD barrier (124) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole (106). A sputter etch is then performed to remove the CVD barrier (124) at the bottom of the via/contact. A second barrier (126) is deposited after the sputter etch. The second barrier (126) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.
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