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公开(公告)号：US20080057711A1
公开(公告)日：2008-03-06
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译： 制造半导体器件，同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。
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公开(公告)号：US07727885B2
公开(公告)日：2010-06-01
申请号：US11511698
申请日：2006-08-29
申请人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
发明人： Phillip Daniel Matz , Sopa Chevacharoenkul , Ching-Te Lin , Basab Chatterjee , Anand Reddy , Kenneth Joseph Newton , Ju-Ai Ruan
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/02063 , H01L21/02164 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/31625 , H01L21/76802 , H01L21/76814 , H01L21/76883
摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
摘要翻译： 制造半导体器件，同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。
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3.发明申请SEMICONDUCTOR DEVICE MANUFACTURED BY REDUCING HILLOCK FORMATION IN METAL INTERCONNECTS 有权通过减少金属互连中的HILLOCK形成制造的半导体器件公开(公告)号：US20080150131A1
公开(公告)日：2008-06-26
申请号：US11614511
申请日：2006-12-21
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L21/02074 , H01L21/76883 , Y10S438/937
摘要： A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
摘要翻译： 一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。 该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。
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4.发明授权Semiconductor device manufactured by reducing hillock formation in metal interconnects 有权通过减少金属互连中的小丘形成制造的半导体器件公开(公告)号：US07745335B2
公开(公告)日：2010-06-29
申请号：US11614511
申请日：2006-12-21
IPC分类号： H01L21/4763 , H01L21/44 , B05D3/00
CPC分类号： H01L21/02074 , H01L21/76883 , Y10S438/937
摘要： A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
摘要翻译： 一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。 该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。
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5.发明申请METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS 审中-公开在VLSI CU互连中防止本地化电气开关引线的方法公开(公告)号：US20100120242A1
公开(公告)日：2010-05-13
申请号：US12266596
申请日：2008-11-07
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/7684 , H01L21/321 , H01L21/3212 , H01L21/76813 , H01L21/76877
摘要： One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More particularly, a semiconductor body comprising one or more exposed copper metal levels is coated with a benzotriazole (BTA) solution. The semiconductor body is then dried, resulting in a protective layer of BTA coating the copper metal levels. The protective layer of BTA passivates the exposed copper surface by forming a protective BTA layer that prevents the copper metal level from coming into direct contact with deionized water thereby preventing copper metal dissolution and providing improved integrated chip yields and reliability.
摘要翻译： 本发明的一个实施例涉及一种用于在金属互连线制造期间由于局部铜溶解形成电开路的方法。 更具体地，包含一种或多种暴露的铜金属水平的半导体主体用苯并三唑（BTA）溶液涂覆。 然后干燥半导体体，得到涂覆铜金属层的BTA保护层。 BTA的保护层通过形成防止铜金属水平与去离子水直接接触的保护性BTA层来钝化暴露的铜表面，从而防止铜金属溶解并提供改进的集成芯片产量和可靠性。
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公开(公告)号：US08334190B2
公开(公告)日：2012-12-18
申请号：US12776057
申请日：2010-05-07
IPC分类号： H01L21/763 , H01L21/302
CPC分类号： C09G1/02 , H01L21/31053 , H01L21/3212 , H01L22/12 , H01L22/26
摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer > a RR for the silicon oxide layer > a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.
摘要翻译： 一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔 延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。 继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。
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公开(公告)号：US20110275168A1
公开(公告)日：2011-11-10
申请号：US12776057
申请日：2010-05-07
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： C09G1/02 , H01L21/31053 , H01L21/3212 , H01L22/12 , H01L22/26
摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.
摘要翻译： 一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔 延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。 继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。
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8.发明授权Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes 有权使用金属绝缘体金属电容器形成集成电路器件，使用顶部电极的选择性蚀刻公开(公告)号：US08110414B2
公开(公告)日：2012-02-07
申请号：US12433042
申请日：2009-04-30
申请人： Marshall O. Cathey, Jr. , Pushpa Mahalingam , Weidong Tian , David C. Guiling , Xinfen Chen , Binghua Hu , Sopa Chevacharoenkul
发明人： Marshall O. Cathey, Jr. , Pushpa Mahalingam , Weidong Tian , David C. Guiling , Xinfen Chen , Binghua Hu , Sopa Chevacharoenkul
CPC分类号： H01L27/0805 , H01L22/26 , H01L28/40
摘要： A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is
摘要翻译： 一种形成具有至少一个金属绝缘体金属（MIM）电容器的集成电路（IC）的方法。 底部电极形成在基板的半导体表面的预定区域上。 在底部电极上形成至少一层包括硅的电介质层，其中电介质层的厚度<1000。在电介质层上形成顶部电极层。 在顶部电极层上形成图案化掩模层。 至少部分地使用干法刻蚀的蚀刻用于蚀刻图案化掩模层外部的顶部电极层，以到达介电层，该电介质层去除了介电层厚度的100埃。 干蚀刻工艺包括使用包含气体的第一卤素，包含氟的第二卤素和包含氟的气体和载气。
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