公开(公告)号：US07732345B2

公开(公告)日：2010-06-08

申请号：US11468884

申请日：2006-08-31

申请人： Phillip Daniel Matz ,  Trace Hurd

发明人： Phillip Daniel Matz ,  Trace Hurd

IPC分类号： H01L21/302

CPC分类号： H01L21/02063

摘要： The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

摘要翻译： 本发明提供一种用于制造集成电路的方法。 在一个实施例中，该方法包括使用蚀刻工具蚀刻衬底内的一个或多个开口，以及对一个或多个开口进行蚀刻后清洁，其中在从蚀刻工具移除衬底和经历 一个或多个打开到蚀刻后的清洁。 该方法可以进一步包括将经过蚀刻后清洁的衬底暴露于漂洗剂，其中基于延迟时间选择漂洗剂的电阻率。

公开(公告)号：US20080057730A1

公开(公告)日：2008-03-06

申请号：US11468884

申请日：2006-08-31

申请人： Phillip Daniel Matz ,  Trace Hurd

发明人： Phillip Daniel Matz ,  Trace Hurd

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02063

摘要： The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

摘要翻译： 本发明提供一种用于制造集成电路的方法。 在一个实施例中，该方法包括使用蚀刻工具蚀刻衬底内的一个或多个开口，以及对一个或多个开口进行蚀刻后清洁，其中在从蚀刻工具移除衬底和经历 一个或多个打开到蚀刻后的清洁。 该方法可以进一步包括将经过蚀刻后清洁的衬底暴露于漂洗剂，其中基于延迟时间选择漂洗剂的电阻率。

公开(公告)号：US20100120242A1

公开(公告)日：2010-05-13

申请号：US12266596

申请日：2008-11-07

申请人： Sopa Chevacharoenkul ,  Phillip Daniel Matz

发明人： Sopa Chevacharoenkul ,  Phillip Daniel Matz

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7684 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/76813 ,  H01L21/76877

摘要： One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More particularly, a semiconductor body comprising one or more exposed copper metal levels is coated with a benzotriazole (BTA) solution. The semiconductor body is then dried, resulting in a protective layer of BTA coating the copper metal levels. The protective layer of BTA passivates the exposed copper surface by forming a protective BTA layer that prevents the copper metal level from coming into direct contact with deionized water thereby preventing copper metal dissolution and providing improved integrated chip yields and reliability.

摘要翻译： 本发明的一个实施例涉及一种用于在金属互连线制造期间由于局部铜溶解形成电开路的方法。 更具体地，包含一种或多种暴露的铜金属水平的半导体主体用苯并三唑（BTA）溶液涂覆。 然后干燥半导体体，得到涂覆铜金属层的BTA保护层。 BTA的保护层通过形成防止铜金属水平与去离子水直接接触的保护性BTA层来钝化暴露的铜表面，从而防止铜金属溶解并提供改进的集成芯片产量和可靠性。

公开(公告)号：US07727885B2

公开(公告)日：2010-06-01

申请号：US11511698

申请日：2006-08-29

申请人： Phillip Daniel Matz ,  Sopa Chevacharoenkul ,  Ching-Te Lin ,  Basab Chatterjee ,  Anand Reddy ,  Kenneth Joseph Newton ,  Ju-Ai Ruan

发明人： Phillip Daniel Matz ,  Sopa Chevacharoenkul ,  Ching-Te Lin ,  Basab Chatterjee ,  Anand Reddy ,  Kenneth Joseph Newton ,  Ju-Ai Ruan

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76883

摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

摘要翻译： 制造半导体器件，同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。

公开(公告)号：US20080057711A1

公开(公告)日：2008-03-06

申请号：US11511698

申请日：2006-08-29

申请人： Phillip Daniel Matz ,  Sopa Chevacharoenkul ,  Ching-Te Lin ,  Basab Chatterjee ,  Anand Reddy ,  Kenneth Joseph Newton ,  Ju-Ai Ruan

发明人： Phillip Daniel Matz ,  Sopa Chevacharoenkul ,  Ching-Te Lin ,  Basab Chatterjee ,  Anand Reddy ,  Kenneth Joseph Newton ,  Ju-Ai Ruan

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76883

摘要： A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

摘要翻译： 制造半导体器件，同时减轻金属化层中的导电空隙形成。 提供基板。 第一电介质层形成在衬底上。 在第一电介质层内形成导电沟槽。 在第一介电层上形成蚀刻停止层。 在蚀刻停止层上/上形成第二介电层。 在器件上形成抗蚀剂掩模，并且在第二介电层中蚀刻通孔。 抗蚀剂掩模通过灰过程去除。 执行清洁处理，其减轻/减少蚀刻停止层的暴露部分上的表面电荷。 采用附加的表面电荷还原技术。 通孔开口填充有导电材料，并执行平面化处理以去除多余的填充材料。