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    Processor core and multiplier that support both vector and single value multiplication
    1.
    发明授权
    Processor core and multiplier that support both vector and single value multiplication 有权
    处理器核心和乘数，支持向量和单值乘法

    公开(公告)号：US08234326B2

    公开(公告)日：2012-07-31

    申请号：US11121945

    申请日：2005-05-05

    申请人： Chinh N. Tran

    发明人： Chinh N. Tran

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5318 ,  G06F2207/3828

    摘要： The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.

    摘要翻译： 本发明提供了支持通用处理器（GPP）和数字信号处理器（DSP）特征的处理系统，装置和方法，例如向量和单值乘法。 在一个实施例中，支持分数算术，整数算术，饱和度和单指令多数据（SIMD）操作，例如向量乘法，乘法累加，点乘积累加和乘法乘法累加。 在一个实施例中，过程核心和/或乘数通过为每个期望的产品创建部分积来乘以向量值或单个值。 这些部分产品被添加以产生中间结果，其以不同的方式组合以支持各种GPP和DSP操作。

    Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding
    2.
    发明授权
    Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding 有权
    处理器核心和乘法器，通过在展位重新编码中反转符号位来支持乘法和差分运算

    公开(公告)号：US08229991B2

    公开(公告)日：2012-07-24

    申请号：US11122004

    申请日：2005-05-05

    申请人： Chinh N. Tran

    发明人： Chinh N. Tran

    IPC分类号： G06F7/52 ,  G06F7/38

    CPC分类号： G06F7/5318 ,  G06F7/5443 ,  G06F2207/3828

    摘要： The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.

    摘要翻译： 本发明提供了支持通用处理器（GPP）和数字信号处理器（DSP）特征的处理系统，装置和方法，例如向量和单值乘法。 在一个实施例中，支持分数算术，整数算术，饱和度和单指令多数据（SIMD）操作，例如向量乘法，乘法累加，点乘积累加和乘法乘法累加。 在一个实施例中，过程核心和/或乘数通过为每个期望的产品创建部分积来乘以向量值或单个值。 这些部分产品被添加以产生中间结果，其以不同的方式组合以支持各种GPP和DSP操作。

    Thin-film composite membrane
    3.
    发明授权
    Thin-film composite membrane 失效
    薄膜复合膜

    公开(公告)号：US5234598A

    公开(公告)日：1993-08-10

    申请号：US882396

    申请日：1992-05-13

    申请人： Chinh N. Tran ,  Adrian C. Maldonado ,  Ratnasamy Somanathan

    发明人： Chinh N. Tran ,  Adrian C. Maldonado ,  Ratnasamy Somanathan

    IPC分类号： B01D69/12 ,  B01D71/56 ,  B01D71/60

    CPC分类号： B01D69/125 ,  B01D71/56

    摘要： A thin-film seimpermeable composite membrane employs the reaction product of N-alkyl phenylenediamine or N,N'-dialkyl phenylenediamine and a poly acyl halide, such as trimesoyl chloride. Preferably the membrane is post-treated with an acid solution followed by an aqueous solution of polyvinyl alcohol and a buffer and/or base to improve its physical properties.

    摘要翻译： 薄膜渗透性复合膜采用N-烷基苯二胺或N，N'-二烷基苯二胺与聚酰卤如均苯三甲酰氯的反应产物。 优选地，用酸溶液，随后用聚乙烯醇的水溶液和缓冲剂和/或碱对膜进行后处理以改善其物理性能。

    Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
    7.
    发明授权
    Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication 失效
    分支预测单元，其使用更少数量的分支预测和替代目标指示来近似更大数量的分支预测

    公开(公告)号：US5974542A

    公开(公告)日：1999-10-26

    申请号：US960818

    申请日：1997-10-30

    申请人： Chinh N. Tran ,  W. Kurt Lewchuk

    发明人： Chinh N. Tran ,  W. Kurt Lewchuk

    IPC分类号： G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch prediction unit includes a cache-line based branch prediction storage having a branch prediction storage location assigned to each cache line of an instruction cache within the microprocessor employing the branch prediction unit. Although each branch prediction storage location is assigned to a particular cache line, the branch prediction storage location stores an alternate target indication indicating whether a branch prediction within the storage location corresponds to a branch instruction within the cache line to which the storage location is assigned or to a branch instruction within a different cache line. The different cache line has a predetermined relationship to the cache line to which the storage location is assigned. In various embodiments, the different cache line is at an index one less than the index of the storage location or is within a different way of the same index. The branch prediction unit described herein approximates having multiple branch predictions per cache line even though only one branch prediction storage location is assigned to the cache line. In cases in which a branch prediction would have been unused due to a lack of sufficient predicted-taken branch instructions within a cache line, the unused branch prediction may be used by a different cache line having a large number of branch instructions.

    摘要翻译： 分支预测单元包括基于高速缓存行的分支预测存储器，其具有分配给使用分支预测单元的微处理器内的指令高速缓存行的每个高速缓存行的分支预测存储位置。 虽然分支预测存储位置被分配给特定的高速缓存行，但是分支预测存储位置存储指示存储位置内的分支预测是否对应于分配存储位置的高速缓存行内的分支指令的替代目标指示，或者 到不同高速缓存行中的分支指令。 不同的高速缓存行与分配存储位置的高速缓存线具有预定的关系。 在各种实施例中，不同的高速缓存线的索引值小于存储位置的索引，或者处于相同索引的不同方式。 即使只有一个分支预测存储位置被分配给高速缓存线，这里描述的分支预测单元近似于每个高速缓存行具有多个分支预测。 在由于在高速缓存线内缺少足够的预测分支指令而不能使用分支预测的情况下，未使用的分支预测可以由具有大量分支指令的不同高速缓存线路使用。

    Pseudo-round-robin arbitration for a shared resource system providing fairness and high throughput
    9.
    发明授权
    Pseudo-round-robin arbitration for a shared resource system providing fairness and high throughput 失效
    共享资源系统的伪循环仲裁提供了公平和高吞吐量

    公开(公告)号：US5519837A

    公开(公告)日：1996-05-21

    申请号：US282332

    申请日：1994-07-29

    申请人： Chinh N. Tran

    发明人： Chinh N. Tran

    IPC分类号： G06F13/362 ,  G06F13/364 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： Systems and methods for arbitrating access to shared resources in a computer system, the systems and methods providing fairness, high throughput, timely response and area efficient implementation. In one form, the pseudo-round-robin arbitration system is composed of a binary tree architecture of round-robin cells. The requests are combined in various groupings and simultaneously provided to all the cells in the multiple levels of the hierarchy. The grant signals are generated from the lowest level of cells. The hierarchy defines that the outputs of the higher level cells serve as enablements to successively related lower level cells in progression by level. A preferred cell for the binary version of the pseudo-round-robin tree architecture is composed of two OR type gates and two AND type gates, the latter gates receiving the enablement signal from the cell in the next higher level of the tree.

    摘要翻译： 用于在计算机系统中仲裁访问共享资源的系统和方法，系统和方法提供公平性，高吞吐量，及时响应和区域有效的实施。 在一种形式中，伪循环仲裁系统由循环单元的二叉树结构组成。 请求被组合在不同的分组中，同时提供给层次结构的多个级别中的所有单元。 授权信号是从最低级别的单元格生成的。 层次结构定义了较高级别单元的输出用作逐级逐级连续相关的较低级别单元的启用。 伪循环树架构的二进制版本的优选小区由两个OR型门和两个AND类型门组成，后一个门从树的下一较高级别的小区接收使能信号。

    Chlorine-resistant semipermeable membranes
    10.
    发明授权
    Chlorine-resistant semipermeable membranes 失效
    耐氯半透膜

    公开(公告)号：US4830885A

    公开(公告)日：1989-05-16

    申请号：US59295

    申请日：1987-06-08

    申请人： Chinh N. Tran ,  Hong C. Chu ,  William G. Light

    发明人： Chinh N. Tran ,  Hong C. Chu ,  William G. Light

    IPC分类号： G05B13/02 ,  B01D20060101 ,  B01D67/00 ,  B01D69/12 ,  B01D71/58 ,  G05B5/01 ,  G05D17/02 ,  H02P29/00

    CPC分类号： G05B5/01 ,  B01D69/125 ,  Y10T428/31536

    摘要： Chlorine-resistant semipermeable membranes which comprise an interfacial polymerized reaction product composite on a porous support backing material may be prepared by contacting a porous support material such as polysulfone with an aqueous solution of an aromatic polyamine, said aqueous solution containing a polyhydric compound and an acid acceptor. The coated support material is then contacted with an organic solvent solution of an aromatic polycarboxylic acid halide for a period of time sufficient to form an interfacial polymerized reaction product on the surface of the support material. The resulting composite is then post treated by washing with an alkaline compound, leaching with sodium bisulfite and treating the leached composite with a polyhydric compound. The resultant membrane composite may be used in separation processes such as the desalination of brackish or sea water, trhe membrane being resistant to attack by chlorine which is present in the water.

    摘要翻译： 在多孔支撑背衬材料上包含界面聚合反应产物复合材料的耐氯半透膜可以通过将多孔载体材料如聚砜与芳族多胺的水溶液接触来制备，所述水溶液含有多羟基化合物和酸 受体。 然后将涂覆的载体材料与芳族多元羧酸卤化物的有机溶剂溶液接触足以在载体材料的表面上形成界面聚合反应产物的时间。 然后将所得复合物用碱性化合物洗涤后处理，用亚硫酸氢钠浸出并用多羟基化合物处理浸出的复合物。 所得到的膜复合物可以用于分离过程，例如咸水或海水的淡化，膜对水中存在的氯的抵抗是抗性的。