公开(公告)号：US20070052463A1

公开(公告)日：2007-03-08

申请号：US11221387

申请日：2005-09-07

申请人： Christopher Abel ,  Abhishek Duggal ,  Peter Metz ,  Vladimir Sindalovsky

发明人： Christopher Abel ,  Abhishek Duggal ,  Peter Metz ,  Vladimir Sindalovsky

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/089 ,  H03L7/093

摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

摘要翻译： 提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。 如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。 累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。 还原步骤可以由例如Σ-Δ调制器进行。 可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。 转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

公开(公告)号：US07330060B2

公开(公告)日：2008-02-12

申请号：US11221387

申请日：2005-09-07

申请人： Christopher J. Abel ,  Abhishek Duggal ,  Peter C. Metz ,  Vladimir Sindalovsky

发明人： Christopher J. Abel ,  Abhishek Duggal ,  Peter C. Metz ,  Vladimir Sindalovsky

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/089 ,  H03L7/093

摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

摘要翻译： 提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。 如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。 累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。 还原步骤可以由例如Σ-Δ调制器进行。 可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。 转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

公开(公告)号：US20070217558A1

公开(公告)日：2007-09-20

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 接收数据流，并使用两个内插器调整时钟信号的相位。 然后使用时钟信号恢复数据流。

公开(公告)号：US20070253477A1

公开(公告)日：2007-11-01

申请号：US11414522

申请日：2006-04-28

申请人： Christopher Abel ,  Mohammad Mobin ,  Gregory Sheets ,  Vladimir Sindalovsky ,  Lane Smith

发明人： Christopher Abel ,  Mohammad Mobin ,  Gregory Sheets ,  Vladimir Sindalovsky ,  Lane Smith

IPC分类号： H03H7/30

CPC分类号： H04L25/062 ,  H04L25/03057

摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.

摘要翻译： 提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。 通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。 偏移锁存器的初始位置可以被放置在例如至少两个轨迹的确定幅度的大约中间。 偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。

公开(公告)号：US20060267660A1

公开(公告)日：2006-11-30

申请号：US11138777

申请日：2005-05-26

申请人： Christopher Abel ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： G06F1/04

CPC分类号： H04L7/0025 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

摘要： A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.

摘要翻译： 延迟环路（例如，电压控制延迟环路）具有（至少）两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件（例如，内插器），其中， 一个内插器正在产生当前被选择用于注入的时钟信号，另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。 这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号，而不是依赖于单个内插器的实现。

公开(公告)号：US20060267635A1

公开(公告)日：2006-11-30

申请号：US11138703

申请日：2005-05-26

申请人： Peter Metz ,  Vladimir Sindalovsky ,  Lane Smith

发明人： Peter Metz ,  Vladimir Sindalovsky ,  Lane Smith

IPC分类号： G01R29/00

CPC分类号： H03L7/07 ,  H03L7/087 ,  H03L7/097 ,  H03L7/0998 ,  H04L7/033

摘要： A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.

摘要翻译： 电路（例如，接收器）具有延迟环路（例如，电压控制的延迟环路）和至少两个相位检测器（PD），其中每个PD比较由延迟环路产生的不同的时钟信号对。 然后使用不同PD的输出来产生用于调整由延迟环路中的延迟元件提供的延迟的控制信号。 在一个实现中，控制信号指示仅当两个PD同意该调整时才应进行延迟调整。 这种多PD技术可以减少由延迟环使用的参考时钟信号中的非50％占空比产生其多个时钟信号的抖动。

公开(公告)号：US08385493B2

公开(公告)日：2013-02-26

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/02

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20100195777A1

公开(公告)日：2010-08-05

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/033

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被去激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US07724857B2

公开(公告)日：2010-05-25

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20130009679A1

公开(公告)日：2013-01-10

申请号：US13178812

申请日：2011-07-08

申请人： Vladimir Sindalovsky ,  Lane A. Smith ,  Jung Cho

发明人： Vladimir Sindalovsky ,  Lane A. Smith ,  Jung Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/08

摘要： In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.

摘要翻译： 在所描述的实施例中，具有数字爆炸相位检测器（BBPD）的时钟对准系统采用数字实现的滞后。 第一个BBPD被用于相位控制环路，该相位控制环路比较来自两个不同时钟域源的相位，其中一个时钟源源作为相位控制环路的参考时钟。 采用具有延迟参考时钟的第二个BBPD来解决第一个BBPD所看到的模糊相位关系。 检查被定义为第一BBPD和第二BBPD的当前值的矢量的BBPD矢量的初始状态。 基于BBPD矢量的初始状态和后续状态，允许非参考时钟通过相位控制回路的动作自然地移动到锁定状态，或者被迫使其相位顺时针或逆时针旋转以达到锁定状态。