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    STRUCTURE AND LAYOUT OF A FET PRIME CELL
    2.
    发明申请
    STRUCTURE AND LAYOUT OF A FET PRIME CELL 有权
    FET母细胞的结构和布局

    公开(公告)号：US20080076212A1

    公开(公告)日：2008-03-27

    申请号：US11923686

    申请日：2007-10-25

    申请人： Basanth JAGANNATHAN ,  John Pekarik ,  Christopher Schnabel

    发明人： Basanth JAGANNATHAN ,  John Pekarik ,  Christopher Schnabel

    IPC分类号： H01L21/337

    CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

    摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

    摘要翻译： 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。

    STRUCTURE AND LAYOUT OF A FET PRIME CELL
    3.
    发明申请
    STRUCTURE AND LAYOUT OF A FET PRIME CELL 审中-公开
    FET母细胞的结构和布局

    公开(公告)号：US20060071304A1

    公开(公告)日：2006-04-06

    申请号：US10711640

    申请日：2004-09-29

    申请人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

    发明人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

    IPC分类号： H01L23/552

    CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

    摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

    摘要翻译： 提供了由导体包围的FET素电池的结构，装置和方法。 周围导体包括靠近FET的源极布置的衬底接触。 周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。 由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。

    Method for checking the pattern density of a semiconductor chip design with variable checking box size and variable stepping distance
    5.
    发明申请
    Method for checking the pattern density of a semiconductor chip design with variable checking box size and variable stepping distance 审中-公开
    用可变复选框尺寸和可变步距检查半导体芯片设计的图案密度的方法

    公开(公告)号：US20070098247A1

    公开(公告)日：2007-05-03

    申请号：US11260007

    申请日：2005-10-27

    申请人： David Sanderson ,  Christopher Schnabel

    发明人： David Sanderson ,  Christopher Schnabel

    IPC分类号： G06K9/00

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for checking the pattern density of a chip layout is described. Initially, the design area is subdivided into a plurality of large checking boxes. Large portions of the chip are discarded from further checking if they are found to fall within acceptable limits at the more stringent and scaled box size. The box size is successively reduced using an appropriate density for each box size until key problem areas are identified on the chip. After the check of a non-failing area, the reduction in checking box size is determined by the detected pattern density. Once the checking box size approximates that of the checking box size as dictated by the groundrule, the checking box size is fixed to that of the groundrule. Rather than using steps that are of the order of the width of the checking box, the box is stepped in an adaptive manner where the distance stepped is relative to the measured pattern density to guarantee that all the errors are captured and reported, regardless of their location from the origin.

    摘要翻译： 描述了用于检查芯片布局的图案密度的方法。 最初，设计区被细分为多个大的检查箱。 如果发现芯片的大部分在更严格和缩放的盒子尺寸下被发现落在可接受的限度内，则将其丢弃。 对于每个盒子尺寸，使用适当的密度连续地减小盒子尺寸，直到芯片上的关键问题区域被识别。 检查非故障区域后，检测框尺寸的减小由检测到的图案密度确定。 一旦复选框大小接近基本规则所指定的复选框大小的大小，则复选框大小固定为基本尺寸。 而不是使用具有检查箱宽度的顺序的步骤，盒子以自适应方式步进，其中步进的距离相对于测量的图案密度，以保证所有的错误被捕获和报告，而不管它们是 位置从原点。

    BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS
    7.
    发明申请
    BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS 失效
    具有隔离和直接联系的双极晶体管

    公开(公告)号：US20070145533A1

    公开(公告)日：2007-06-28

    申请号：US11677776

    申请日：2007-02-22

    申请人： David AHLGREN ,  Gregory FREEMAN ,  Francois PAGETTE ,  Christopher SCHNABEL ,  Anna TOPOL

    发明人： David AHLGREN ,  Gregory FREEMAN ,  Francois PAGETTE ,  Christopher SCHNABEL ,  Anna TOPOL

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

    摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。

    Fabrication of bipolar transistor having reduced collector-base capacitance
    8.
    发明申请
    Fabrication of bipolar transistor having reduced collector-base capacitance 失效
    具有减小的集电极 - 基极电容的双极晶体管的制造

    公开(公告)号：US20070096259A1

    公开(公告)日：2007-05-03

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.

    摘要翻译： 提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。 外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。 低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。 形成发射极层以覆盖本征基极层。

    BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS
    9.
    发明申请
    BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS 有权
    具有隔离和直接联系的双极晶体管

    公开(公告)号：US20050269664A1

    公开(公告)日：2005-12-08

    申请号：US10709905

    申请日：2004-06-04

    申请人： David Ahlgren ,  Gregory Freeman ,  Francois Pagette ,  Christopher Schnabel ,  Anna Topol

    发明人： David Ahlgren ,  Gregory Freeman ,  Francois Pagette ,  Christopher Schnabel ,  Anna Topol

    IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L29/80

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

    摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。

    Electronic trip unit capable of analog and digital setting of circuit breaker setpoints
    10.
    发明授权
    Electronic trip unit capable of analog and digital setting of circuit breaker setpoints 有权
    电子跳闸单元，能够模拟和数字设置断路器设定值

    公开(公告)号：US06788512B2

    公开(公告)日：2004-09-07

    申请号：US10063371

    申请日：2002-04-16

    申请人： Nataniel B. Vicente ,  Christopher Schnabel ,  Mark Fredrick Culler

    发明人： Nataniel B. Vicente ,  Christopher Schnabel ,  Mark Fredrick Culler

    IPC分类号： H02H308

    CPC分类号： H02H3/006

    摘要： A trip unit is provided with a microcontroller and non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memory, for storing trip setting values, including initializing parameters, boot code, and operational parameters being capable of analog or digital programming depending on a switching instruction. This configuration enables one to change the trip unit's trip setting values after it is manufactured either remotely or locally. The present invention provides thus increased functionality to trip units by enabling upgrades and servicing of the trip unit by downloading replacement trip setting values to it and having multiple operational parameters (trip setting values) available. This would include locally altering trip setting values and remotely downloading trip setting values when the electronic trip unit is connected to a host controller, such as a multi-purpose computer either directly, over the telephone lines, LAN or any other suitable connection such as the Internet.

    摘要翻译： 跳闸单元配有微控制器和非易失性存储器，例如EEPROM（电可擦除可编程只读存储器）或闪存，用于存储跳闸设置值，包括初始化参数，启动代码和能够进行模拟或 数字编程取决于切换指令。 该配置可以在远程或本地制造之后更改跳闸单元的跳闸设置值。 本发明通过下载替代跳闸设置值并且具有多个可用的操作参数（跳闸设置值）来实现对跳闸单元的升级和维护，从而提高了跳闸单元的功能。 这将包括当电子跳闸单元通过电话线，LAN或任何其它合适的连接如电话线路连接到诸如多功能计算机的主机控制器（例如多用途计算机）时，本地更改行程设置值和远程下载行程设置值 互联网。