公开(公告)号：US20050272195A1

公开(公告)日：2005-12-08

申请号：US11186748

申请日：2005-07-21

申请人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

发明人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8232

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US20050001273A1

公开(公告)日：2005-01-06

申请号：US10604206

申请日：2003-07-01

申请人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

发明人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L33/00

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US07355221B2

公开(公告)日：2008-04-08

申请号：US10908448

申请日：2005-05-12

申请人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

发明人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

公开(公告)号：US20080076212A1

公开(公告)日：2008-03-27

申请号：US11923686

申请日：2007-10-25

申请人： Basanth JAGANNATHAN ,  John Pekarik ,  Christopher Schnabel

发明人： Basanth JAGANNATHAN ,  John Pekarik ,  Christopher Schnabel

IPC分类号： H01L21/337

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

摘要翻译： 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。

公开(公告)号：US20060071304A1

公开(公告)日：2006-04-06

申请号：US10711640

申请日：2004-09-29

申请人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

发明人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

IPC分类号： H01L23/552

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

摘要翻译： 提供了由导体包围的FET素电池的结构，装置和方法。 周围导体包括靠近FET的源极布置的衬底接触。 周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。 由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。

公开(公告)号：US20070026598A1

公开(公告)日：2007-02-01

申请号：US11161337

申请日：2005-07-29

申请人： John Pekarik ,  Xudong Wang

发明人： John Pekarik ,  Xudong Wang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L29/045

摘要： A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.

摘要翻译： 在集成电路的器件特性中实现期望偏移的方法包括在具有第一晶格取向的衬底的第一部分上形成第一导电类型的第一器件，以及在第一导电类型的第一部分上形成第一导电类型的第二器件 所述基板的第二部分具有第二晶格取向。 形成在第一晶格取向上的第一器件的载流子迁移率大于在第二晶格取向上形成的第二器件的载流子迁移率。

公开(公告)号：US20060289994A1

公开(公告)日：2006-12-28

申请号：US11160463

申请日：2005-06-24

申请人： David Greenberg ,  John Pekarik ,  Jorg Scholvin

发明人： David Greenberg ,  John Pekarik ,  Jorg Scholvin

IPC分类号： H01L23/52

CPC分类号： H01L23/528 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

摘要翻译： 用于集成电路芯片的多层金属化布局包括具有金属化布局连接的第一，第二和第三元件的晶体管。 该布局使包括电迁移在内的电流限制机制最小化，从而将第二触点的连接从芯片垂直定位，将金属化布局的平面和手指重叠到第一和第二元件，并形成多层金属化层的金字塔或楼梯以平滑对角线电流 流。

公开(公告)号：US20060255415A1

公开(公告)日：2006-11-16

申请号：US10908448

申请日：2005-05-12

申请人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

发明人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。