-
1.发明申请Method for checking the pattern density of a semiconductor chip design with variable checking box size and variable stepping distance 审中-公开用可变复选框尺寸和可变步距检查半导体芯片设计的图案密度的方法公开(公告)号：US20070098247A1
公开(公告)日：2007-05-03
申请号：US11260007
申请日：2005-10-27
IPC分类号： G06K9/00
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method for checking the pattern density of a chip layout is described. Initially, the design area is subdivided into a plurality of large checking boxes. Large portions of the chip are discarded from further checking if they are found to fall within acceptable limits at the more stringent and scaled box size. The box size is successively reduced using an appropriate density for each box size until key problem areas are identified on the chip. After the check of a non-failing area, the reduction in checking box size is determined by the detected pattern density. Once the checking box size approximates that of the checking box size as dictated by the groundrule, the checking box size is fixed to that of the groundrule. Rather than using steps that are of the order of the width of the checking box, the box is stepped in an adaptive manner where the distance stepped is relative to the measured pattern density to guarantee that all the errors are captured and reported, regardless of their location from the origin.
摘要翻译： 描述了用于检查芯片布局的图案密度的方法。 最初，设计区被细分为多个大的检查箱。 如果发现芯片的大部分在更严格和缩放的盒子尺寸下被发现落在可接受的限度内，则将其丢弃。 对于每个盒子尺寸，使用适当的密度连续地减小盒子尺寸，直到芯片上的关键问题区域被识别。 检查非故障区域后，检测框尺寸的减小由检测到的图案密度确定。 一旦复选框大小接近基本规则所指定的复选框大小的大小，则复选框大小固定为基本尺寸。 而不是使用具有检查箱宽度的顺序的步骤，盒子以自适应方式步进，其中步进的距离相对于测量的图案密度，以保证所有的错误被捕获和报告，而不管它们是 位置从原点。
-
2.发明申请STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED COLLECTOR-BASED CAPACITANCE 失效具有减少集电极电容的双极晶体管的结构和方法公开(公告)号：US20050212087A1
公开(公告)日：2005-09-29
申请号：US10708860
申请日：2004-03-29
IPC分类号： H01L21/331 , H01L27/102 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译： 提供了用于形成双极晶体管的结构和方法。 如所公开的，提供覆盖在集电极层上的本征基层。 低电容区域横向设置在集电极层附近。 低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。 发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。
-
公开(公告)号：US20080076212A1
公开(公告)日：2008-03-27
申请号：US11923686
申请日：2007-10-25
IPC分类号： H01L21/337
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译： 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。
-
公开(公告)号：US20060071304A1
公开(公告)日：2006-04-06
申请号：US10711640
申请日：2004-09-29
IPC分类号： H01L23/552
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.
摘要翻译： 提供了由导体包围的FET素电池的结构，装置和方法。 周围导体包括靠近FET的源极布置的衬底接触。 周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。 由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。
-
5.发明授权Method, computer program product, and system for merging multiple same class instance states 失效方法，计算机程序产品和用于合并多个相同类的实例状态的系统公开(公告)号：US08056073B2
公开(公告)日：2011-11-08
申请号：US11970734
申请日：2008-01-08
CPC分类号： G06F8/34 , G06F9/4488
摘要： A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.
摘要翻译： 一种方法，计算机程序产品和系统，用于使得能够将多个实例变量合并到具有由用户确定的值的相同实例变量的新的复合同类实例中。 相同类的实例以表格格式排列，并提供有选择按钮，以允许用户选择所需的实例变量值。
-
6.发明申请METHOD, COMPUTER PROGRAM PRODUCT, AND SYSTEM FOR MERGING MULTIPLE SAME CLASS INSTANCE STATES 失效方法，计算机程序产品和用于合并多个类别实例状态的系统公开(公告)号：US20090178024A1
公开(公告)日：2009-07-09
申请号：US11970734
申请日：2008-01-08
IPC分类号： G06F9/44
CPC分类号： G06F8/34 , G06F9/4488
摘要： A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.
摘要翻译： 一种方法，计算机程序产品和系统，用于使得能够将多个实例变量合并到具有由用户确定的值的相同实例变量的新的复合同类实例中。 相同类的实例以表格格式排列，并提供有选择按钮，以允许用户选择所需的实例变量值。
-
7.发明申请Fabrication of bipolar transistor having reduced collector-base capacitance 失效具有减小的集电极 - 基极电容的双极晶体管的制造公开(公告)号：US20070096259A1
公开(公告)日：2007-05-03
申请号：US11633380
申请日：2006-12-04
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.
摘要翻译： 提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。 外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。 低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。 形成发射极层以覆盖本征基极层。
-
公开(公告)号：US20050269664A1
公开(公告)日：2005-12-08
申请号：US10709905
申请日：2004-06-04
IPC分类号： H01L21/331 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。
-
9.发明授权Electronic trip unit capable of analog and digital setting of circuit breaker setpoints 有权电子跳闸单元，能够模拟和数字设置断路器设定值公开(公告)号：US06788512B2
公开(公告)日：2004-09-07
申请号：US10063371
申请日：2002-04-16
IPC分类号： H02H308
CPC分类号： H02H3/006
摘要： A trip unit is provided with a microcontroller and non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memory, for storing trip setting values, including initializing parameters, boot code, and operational parameters being capable of analog or digital programming depending on a switching instruction. This configuration enables one to change the trip unit's trip setting values after it is manufactured either remotely or locally. The present invention provides thus increased functionality to trip units by enabling upgrades and servicing of the trip unit by downloading replacement trip setting values to it and having multiple operational parameters (trip setting values) available. This would include locally altering trip setting values and remotely downloading trip setting values when the electronic trip unit is connected to a host controller, such as a multi-purpose computer either directly, over the telephone lines, LAN or any other suitable connection such as the Internet.
摘要翻译： 跳闸单元配有微控制器和非易失性存储器，例如EEPROM（电可擦除可编程只读存储器）或闪存，用于存储跳闸设置值，包括初始化参数，启动代码和能够进行模拟或 数字编程取决于切换指令。 该配置可以在远程或本地制造之后更改跳闸单元的跳闸设置值。 本发明通过下载替代跳闸设置值并且具有多个可用的操作参数（跳闸设置值）来实现对跳闸单元的升级和维护，从而提高了跳闸单元的功能。 这将包括当电子跳闸单元通过电话线，LAN或任何其它合适的连接如电话线路连接到诸如多功能计算机的主机控制器（例如多用途计算机）时，本地更改行程设置值和远程下载行程设置值 互联网。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.02 秒)
