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    Fabrication of bipolar transistor having reduced collector-base capacitance
    1.
    发明申请
    Fabrication of bipolar transistor having reduced collector-base capacitance 失效
    具有减小的集电极 - 基极电容的双极晶体管的制造

    公开(公告)号：US20070096259A1

    公开(公告)日：2007-05-03

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher Schnabel ,  William Tonti

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.

    摘要翻译： 提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。 外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。 低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。 形成发射极层以覆盖本征基极层。

    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
    3.
    发明申请
    STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
    带有收集器的自对准双极晶体管的结构和方法

    公开(公告)号：US20050184359A1

    公开(公告)日：2005-08-25

    申请号：US10708340

    申请日：2004-02-25

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

    摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

    摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

    Method of fabricating a bipolar transistor having reduced collector-base capacitance
    4.
    发明授权
    Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
    制造具有减小的集电极 - 基极电容的双极晶体管的方法

    公开(公告)号：US07462547B2

    公开(公告)日：2008-12-09

    申请号：US11633380

    申请日：2006-12-04

    申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

    IPC分类号： H01L21/331 ,  H01L27/082

    CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

    摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

    摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定 具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

    METHOD FOR FORMING A BIPOLAR TRANSISTOR DEVICE WITH SELF-ALIGNED RAISED EXTRINSIC BASE
    8.
    发明申请
    METHOD FOR FORMING A BIPOLAR TRANSISTOR DEVICE WITH SELF-ALIGNED RAISED EXTRINSIC BASE 有权
    形成具有自对准基极化基极的双极晶体管器件的方法

    公开(公告)号：US20080078997A1

    公开(公告)日：2008-04-03

    申请号：US11866440

    申请日：2007-10-03

    申请人： Marwan Khater

    发明人： Marwan Khater

    IPC分类号： H01L29/04

    CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242

    摘要： Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

    摘要翻译： 公开了制造具有自对准凸起外部基极的双极晶体管的方法的实施例。 在该方法中，在具有最小尺寸的基板上形成介质垫，该最小尺寸能够使用当前的光刻图案来生产。 开口在电介质垫的上方对准，并通过隔离氧化层蚀刻到外在的基层。 开口的尺寸等于或大于电介质垫。 通过外部基极层蚀刻另一个较小的开口到电介质垫。 使用多步蚀刻工艺来从介电垫的表面选择性地去除非本征基层，然后选择性地去除介电垫。 然后在所得沟槽中形成发射极。 所得到的晶体管结构在发射极的下部边缘与外部基极的边缘之间具有最小化的距离，从而降低电阻。

    Bipolar transistor with collector having an epitaxial Si:C region
    9.
    发明申请
    Bipolar transistor with collector having an epitaxial Si:C region 失效
    具有集电极的双极晶体管具有外延Si：C区域

    公开(公告)号：US20060289852A1

    公开(公告)日：2006-12-28

    申请号：US11511047

    申请日：2006-08-28

    申请人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

    发明人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

    IPC分类号： H01L31/00

    CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

    摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

    摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION
    10.
    发明申请
    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION 有权
    制造具有非对称应力通道区域的场效应晶体管的结构和方法

    公开(公告)号：US20060255415A1

    公开(公告)日：2006-11-16

    申请号：US10908448

    申请日：2005-05-12

    申请人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    发明人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

    摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

    摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。