公开(公告)号：US06943120B1

公开(公告)日：2005-09-13

申请号：US10055095

申请日：2002-01-23

Applicant: Chuan-Chieh Huang ,  Feng-Yueh Chang ,  Chi-Lien Lin

Inventor： Chuan-Chieh Huang ,  Feng-Yueh Chang ,  Chi-Lien Lin

IPC: H01L21/302

CPC classification number: H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L2221/1063

Abstract: A method of forming a narrow diameter opening in an insulator layer, featuring a vertical shape profile, has been developed. Using a photoresist shape as an etch mask a first plasma procedure is used to form an initial opening, with a tapered profile shape, in the insulator layer exposing a portion of the top surface of an underlying stop layer. The first plasma procedure results in formation of a thin polymer layer located at the bottom of the initial opening. A second plasma procedure performed in situ, results in deposition of additional polymer layer, comprised of carbon and fluorine, at the bottom of the initial opening. This is followed by a third plasma procedure, performed in situ in an oxygen plasma, removing polymer and releasing fluorine based radicals which etch portions of insulator layer exposed at the bottom of the initial opening, resulting in a final opening featuring a vertical profile shape.

Abstract translation: 已经开发了在绝缘体层中形成具有垂直形状轮廓的窄直径开口的方法。 使用光致抗蚀剂形状作为蚀刻掩模，使用第一等离子体程序在绝缘体层中形成具有锥形轮廓形状的初始开口，暴露下面停止层的顶表面的一部分。 第一个等离子体程序导致位于初始开口底部的薄聚合物层的形成。 原位执行的第二个等离子体工艺导致在初始开口的底部沉积由碳和氟组成的另外的聚合物层。 之后是第三等离子体工艺，在氧等离子体中原位进行，去除聚合物并释放氟基，其蚀刻暴露在初始开口底部的绝缘体层的部分，产生具有垂直外形形状的最终开口。

公开(公告)号：US06566184B1

公开(公告)日：2003-05-20

申请号：US10082015

申请日：2002-02-21

Applicant: Zin-Chein Wei ,  Chuan-Chieh Huang ,  Chih-Hsiung Lee

Inventor： Zin-Chein Wei ,  Chuan-Chieh Huang ,  Chih-Hsiung Lee

IPC: H01L218238

CPC classification number: H01L21/823842

Abstract: A method of fabricating doped polysilicon structures comprising the following steps. A substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

Abstract translation: 一种制造掺杂多晶硅结构的方法，包括以下步骤。 提供衬底并且在衬底上形成未掺杂的多晶硅层。 将未掺杂多晶硅层图案化以在N区内形成至少一个未掺杂的多晶硅结构，以及在P区内形成至少一个未掺杂的多晶硅结构。 在N区域内的至少一个未掺杂的多晶硅结构被掩蔽，在P区域内露出另一个至少一个未掺杂的多晶硅结构的上部。 在P区内暴露的至少一个未掺杂的多晶硅结构被掺杂以形成P掺杂的多晶硅结构。 在N区域内被掩蔽的至少一个未掺杂的多晶硅结构的上部被屏蔽和暴露，并且P掺杂多晶硅结构被掩蔽。 在N区域内暴露的至少一个未掺杂多晶硅结构被掺杂以形成N掺杂多晶硅结构以完成掺杂多晶硅结构的制造。

公开(公告)号：US07015089B2

公开(公告)日：2006-03-21

申请号：US10289761

申请日：2002-11-07

Applicant: Jyh-Shiou Hsu ,  Pin-Yi Hsin ,  Chuan-Chieh Huang

Inventor： Jyh-Shiou Hsu ,  Pin-Yi Hsin ,  Chuan-Chieh Huang

IPC: H01L21/8242

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/823425 ,  H01L27/105 ,  H01L27/1052

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%–90% of the RPO film thickness and wet etching is used to remove the remaining 10%–30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract translation: 描述了抗蚀剂保护电介质层和优选保护性二氧化硅层的改进方法。 该方法由两个连续蚀刻步骤组成，第一个是定时等离子体蚀刻工艺，第二个是定时湿蚀刻工艺。 使用等离子体蚀刻去除大约70％-90％的RPO膜厚度，并且使用湿蚀刻来除去剩余的10％-30％的膜厚度。 两步蚀刻工艺实现了优异的尺寸控制，抗蚀剂掩模下的非底切轮廓，并防止了抗蚀剂掩模剥离在掩模/ RPO膜界面处的粘附失败。 在制造半导体器件的工艺流程中使用RPO膜时，改进的方法具有广泛的应用。

公开(公告)号：US06767844B2

公开(公告)日：2004-07-27

申请号：US10190412

申请日：2002-07-03

Applicant: Chuan-Chieh Huang

Inventor： Chuan-Chieh Huang

IPC: H01L2131

CPC classification number: H01L21/67248 ,  H01J37/32642 ,  H01L21/67069 ,  H01L21/67109

Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.

公开(公告)号：US06642150B1

公开(公告)日：2003-11-04

申请号：US09473029

申请日：1999-12-28

Applicant: Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

Inventor： Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

IPC: H01L21302

CPC classification number: H01L22/24 ,  G01N21/95692 ,  H01L22/34

Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Abstract translation: 用于检测多芯片半导体测试晶片的接触层中的盲孔的新方法利用以下事实：如果孔不是盲孔，则随后的蚀刻步骤将孔延伸到紧邻下面的层中的预定距离 接触层。 在已经通过接触层蚀刻了预定数量的孔并且进入到接触层下面的预定距离之前，剥离接触层以露出下层中的孔。 这些孔由通常检测类似于孔的晶片缺陷的商业设备进行光学扫描。 通过比较测试晶片上不同芯片的孔来检测缺失的孔。 该测试对于高密度等离子体蚀刻特别有用，因为这些孔通常相对于接触层的厚度具有非常小的直径。