公开(公告)号：US20140013036A1

公开(公告)日：2014-01-09

申请号：US13915665

申请日：2013-06-12

申请人： Oh-Seong KWON ,  Chulwoo PARK ,  Yunsang LEE

发明人： Oh-Seong KWON ,  Chulwoo PARK ,  Yunsang LEE

IPC分类号： G11C11/406 ,  G06F12/02 ,  G06F9/44

CPC分类号： G11C11/40615 ,  G06F9/4401 ,  G06F12/0246 ,  G11C5/04 ,  G11C16/3418 ,  G11C2211/4061

摘要： Disclosed is a method of booting a user device including a nonvolatile random access memory (RAM) and a mode register. The method includes reading a Basic Input/Output System (BIOS) refresh setting during a booting operation, and setting the mode register to a refresh timing mode of the nonvolatile RAM according to the BIOS refresh setting. The refresh timing mode selectively includes a refresh inactivation mode for inactivating a refresh operation of the nonvolatile RAM or a refresh execution mode of multiple refresh execution modes having corresponding different refresh periods for activating the refresh operation of the nonvolatile RAM.

摘要翻译： 公开了一种引导包括非易失性随机存取存储器（RAM）和模式寄存器的用户设备的方法。 该方法包括在引导操作期间读取基本输入/输出系统（BIOS）刷新设置，并根据BIOS刷新设置将模式寄存器设置为非易失性RAM的刷新定时模式。 刷新定时模式选择性地包括用于停止非易失性RAM的刷新操作的刷新失活模式或具有用于激活非易失性RAM的刷新操作的相应不同刷新周期的多个刷新执行模式的刷新执行模式。

公开(公告)号：US20130099305A1

公开(公告)日：2013-04-25

申请号：US13586018

申请日：2012-08-15

申请人： Sua KIM ,  Jin Ho Kim ,  Chulwoo Park

发明人： Sua KIM ,  Jin Ho Kim ,  Chulwoo Park

IPC分类号： H01L29/78

CPC分类号： H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2454

摘要： Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided.

摘要翻译： 提供具有垂直沟道晶体管的半导体器件。 半导体器件包括衬底上的绝缘层和绝缘层上的掩埋位线。 埋置的位线沿第一方向延伸。 有源柱设置在掩埋位线上。 有源柱包括下掺杂区域，具有垂直堆叠在掩埋位线上的第一侧壁和上掺杂区的沟道区。 接触栅电极设置成与沟道区的第一侧壁相邻。 字线电连接到接触栅电极。 字线在与第一方向相交的第二方向上延伸。 弦体连接器电连接到通道区域。 还提供了相关方法。

公开(公告)号：US08809926B2

公开(公告)日：2014-08-19

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L21/02

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。

公开(公告)号：US20130043525A1

公开(公告)日：2013-02-21

申请号：US13588513

申请日：2012-08-17

申请人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

发明人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

IPC分类号： H01L29/78

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。

公开(公告)号：US08987811B2

公开(公告)日：2015-03-24

申请号：US13588513

申请日：2012-08-17

申请人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

发明人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

IPC分类号： H01L29/66 ,  H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。

公开(公告)号：US08816432B2

公开(公告)日：2014-08-26

申请号：US13586018

申请日：2012-08-15

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park

IPC分类号： H01L29/66

CPC分类号： H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2454

摘要： Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided.

摘要翻译： 提供具有垂直沟道晶体管的半导体器件。 半导体器件包括衬底上的绝缘层和绝缘层上的掩埋位线。 埋置的位线沿第一方向延伸。 有源柱设置在掩埋位线上。 有源柱包括下掺杂区域，具有垂直堆叠在掩埋位线上的第一侧壁和上掺杂区的沟道区。 接触栅电极设置成与沟道区的第一侧壁相邻。 字线电连接到接触栅电极。 字线在与第一方向相交的第二方向上延伸。 弦体连接器电连接到通道区域。 还提供了相关方法。

公开(公告)号：US20130056812A1

公开(公告)日：2013-03-07

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L29/82

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。