公开(公告)号：US20130043525A1

公开(公告)日：2013-02-21

申请号：US13588513

申请日：2012-08-17

申请人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

发明人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

IPC分类号： H01L29/78

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。

公开(公告)号：US20130260531A1

公开(公告)日：2013-10-03

申请号：US13789930

申请日：2013-03-08

申请人： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

发明人： Jay-Bok CHOI ,  Jiyoung KIM ,  Hyun-Woo CHUNG ,  Sungkwan CHOI ,  Yoosang HWANG

IPC分类号： H01L21/762

CPC分类号： H01L23/5283 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

公开(公告)号：US20140246782A1

公开(公告)日：2014-09-04

申请号：US14141947

申请日：2013-12-27

申请人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

发明人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。

公开(公告)号：US20130087842A1

公开(公告)日：2013-04-11

申请号：US13614457

申请日：2012-09-13

申请人： Jiyoung KIM ,  Yongchul OH ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

发明人： Jiyoung KIM ,  Yongchul OH ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888

摘要： According to example embodiments, a semiconductor device includes a lower active portion protruding from a substrate, an active pillar protruding from the lower active portion, a surround gate electrode surrounding the active pillar, a buried bit line extending along a first direction and being on the lower active portion and electrically connected to the lower active portion, and a contact gate electrode contacting both the surround gate electrode and a word line extending a second direction crossing the first direction.

摘要翻译： 根据示例性实施例，半导体器件包括从基板突出的下部有源部分，从下部有源部分突出的有源柱，围绕有源支柱的环绕栅电极，沿第一方向延伸的掩埋位线， 下部有源部分并且电连接到下部有源部分，以及接触栅极电极，其接触环绕栅极电极和与第一方向交叉的第二方向延伸的字线。

公开(公告)号：US20080173936A1

公开(公告)日：2008-07-24

申请号：US11954135

申请日：2007-12-11

申请人： Jae-Man YOON ,  Yong-Chul OH ,  Hui-Jung KIM ,  Hyun-Woo CHUNG

发明人： Jae-Man YOON ,  Yong-Chul OH ,  Hui-Jung KIM ,  Hyun-Woo CHUNG

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10885 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

摘要翻译： 公开了一种存取装置和半导体装置。 进入装置包括分隔下部源极/漏极区域和上部源极/漏极区域的垂直取向的沟道，设置在沟道上的栅极电介质以及耦合到穿过栅极电介质的沟道的统一的栅电极/连接线，其中， 统一的栅极电极/连接线包括靠近栅极电介质设置并覆盖下部源极/漏极区域的至少一部分的下降的唇部。

公开(公告)号：US20120086066A1

公开(公告)日：2012-04-12

申请号：US13097365

申请日：2011-04-29

申请人： Daeik KIM ,  HyeongSun HONG ,  Yoosang HWANG ,  Hyun-Woo CHUNG

发明人： Daeik KIM ,  HyeongSun HONG ,  Yoosang HWANG ,  Hyun-Woo CHUNG

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/94

摘要： A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.

摘要翻译： 半导体存储器件包括半导体衬底，从半导体衬底延伸的半导体柱，所述半导体柱包括第一区域，第二区域和第三区域，所述第二区域位于第一区域和第三区域之间，第三区域 位于第二区域和半导体衬底之间的区域，具有不同导电类型的紧邻区域，设置在其间具有第一绝缘层的第二区域上的第一栅极图案和设置在第三区域上的第二栅极图案，其中第二区域 通过第二栅极图案欧姆连接到衬底。