利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.023 秒)

    SEMICONDUCTOR DEVICES HAVING WORK FUNCTION METAL FILMS AND TUNING MATERIALS
    1.
    发明申请
    SEMICONDUCTOR DEVICES HAVING WORK FUNCTION METAL FILMS AND TUNING MATERIALS 有权
    具有工作功能金属膜和调谐材料的半导体器件

    公开(公告)号：US20160225868A1

    公开(公告)日：2016-08-04

    申请号：US14989154

    申请日：2016-01-06

    申请人： Wan-Don KIM ,  Oh-Seong KWON ,  Hoon-Joo NA ,  Hyeok-Jun SON ,  Jae-Yeol SONG ,  Sung-Kee HAN ,  Sang-Jin HYUN

    发明人： Wan-Don KIM ,  Oh-Seong KWON ,  Hoon-Joo NA ,  Hyeok-Jun SON ,  Jae-Yeol SONG ,  Sung-Kee HAN ,  Sang-Jin HYUN

    IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L27/088

    CPC分类号： H01L29/4966 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/4238

    摘要： A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

    摘要翻译： 半导体器件包括：第一晶体管，包括在基板上的第一电介质膜和第一电介质膜上的第一导电类型的第一功函数金属膜，第二晶体管，其在基板上包括第二电介质膜，第二功函数金属 第二电介质膜上的第一导电类型的膜，以及在基板上包括第三电介质膜的第三晶体管和在第三介电膜上的第一导电类型的第三功函数金属膜。 第一电介质膜包括功函数调谐材料，第二电介质膜不包括功函调谐材料。 第一功能金属膜的厚度与第三功函数金属膜的厚度不同。 还描述了相关方法。

    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160181412A1

    公开(公告)日：2016-06-23

    申请号：US14963271

    申请日：2015-12-09

    申请人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

    发明人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/088

    CPC分类号： H01L27/088 ,  H01L21/28088 ,  H01L21/82345 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

    摘要： Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.

    摘要翻译： 提供了一种半导体器件，其被配置为通过在阻挡层之间形成氧化物层来阻挡物理扩散路径，以防止杂质通过阻挡层之间的物理扩散路径扩散，以及制造半导体器件的方法。 半导体器件包括：形成在基板上的栅极绝缘层，形成在栅极绝缘层上的第一势垒层，形成在第一势垒层上的氧化物层，氧化物层包括通过氧化包含在第一势垒中的材料形成的氧化物 形成在氧化物层上的第二阻挡层，形成在第二阻挡层上的栅电极和设置在基板中的栅电极的相对侧的源极/漏极。

    Semiconductor device and method for fabricating the same
    6.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09337057B2

    公开(公告)日：2016-05-10

    申请号：US14802467

    申请日：2015-07-17

    申请人： Moon-Kyu Park ,  Oh-Seong Kwon ,  Sung-Kee Han ,  Sang-Jin Hyun

    发明人： Moon-Kyu Park ,  Oh-Seong Kwon ,  Sung-Kee Han ,  Sang-Jin Hyun

    IPC分类号： H01L21/3215 ,  H01L29/40 ,  H01L21/28

    CPC分类号： H01L21/28088 ,  H01L21/3105 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

    摘要： Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.

    摘要翻译： 提供制造半导体器件的方法。 制造半导体器件的方法可以包括在衬底上形成包括沟槽的第一层间绝缘膜，沿着沟槽的内侧壁和底表面形成高k层，形成包含杂质的第一功函数控制膜 高k层，从第一功函数控制膜去除杂质，以使第一功函数控制膜的表面电阻降低约30％至约60％，并在沟槽中形成栅极金属。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160020118A1

    公开(公告)日：2016-01-21

    申请号：US14802467

    申请日：2015-07-17

    申请人： Moon-Kyu PARK ,  Oh-Seong KWON ,  Sung-Kee HAN ,  Sang-Jin HYUN

    发明人： Moon-Kyu PARK ,  Oh-Seong KWON ,  Sung-Kee HAN ,  Sang-Jin HYUN

    IPC分类号： H01L21/3215 ,  H01L21/28 ,  H01L29/40

    CPC分类号： H01L21/28088 ,  H01L21/3105 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

    摘要： Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.

    摘要翻译： 提供制造半导体器件的方法。 制造半导体器件的方法可以包括在衬底上形成包括沟槽的第一层间绝缘膜，沿着沟槽的内侧壁和底表面形成高k层，形成包含杂质的第一功函数控制膜 高k层，从第一功函数控制膜去除杂质，以使第一功函数控制膜的表面电阻降低约30％至约60％，并在沟槽中形成栅极金属。

    Resistive memory device and method of writing data using multi-mode switching current
    8.
    发明授权
    Resistive memory device and method of writing data using multi-mode switching current 有权
    电阻式存储器件及使用多模切换电流写入数据的方法

    公开(公告)号：US08670269B2

    公开(公告)日：2014-03-11

    申请号：US13609330

    申请日：2012-09-11

    申请人： Oh-Seong Kwon ,  Jin-Hyun Kim ,  Hyun-Ho Choi

    发明人： Oh-Seong Kwon ,  Jin-Hyun Kim ,  Hyun-Ho Choi

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C29/50008 ,  G11C11/16 ,  G11C13/00

    摘要： A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current.

    摘要翻译： 在电阻式存储器件中写入数据的方法包括在使用写入电流对正常存储器单元的写入操作期间以及在针对弱存储器单元的弱写入操作期间执行使用以区分正常存储器单元与弱存储器单元的测试操作， 写入电流较高。

    SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF FORMING THE SAME 有权
    具有金属插件的半导体器件及其形成方法

    公开(公告)号：US20120299072A1

    公开(公告)日：2012-11-29

    申请号：US13425906

    申请日：2012-03-21

    申请人： WAN-DON KIM ,  Seung-Hwan Lee ,  Beom-Seok Kim ,  Kyu-Ho Cho ,  Oh-Seong Kwon ,  Geun-Kyu Choi ,  Ji-Eun Lim ,  Yong-Suk Tak

    发明人： WAN-DON KIM ,  Seung-Hwan Lee ,  Beom-Seok Kim ,  Kyu-Ho Cho ,  Oh-Seong Kwon ,  Geun-Kyu Choi ,  Ji-Eun Lim ,  Yong-Suk Tak

    IPC分类号： H01L27/06

    CPC分类号： H01L21/823475 ,  H01L21/823456

    摘要： Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.

    摘要翻译： 提供了包括第一，第二和第三源极/漏极区域的半导体器件。 提供了与第一源/漏区接触的第一导电插塞，具有第一宽度和第一高度，并且包括第一材料。 设置覆盖第一导电插塞和基板的层间绝缘层。 提供垂直穿过层间绝缘层以与具有第二宽度和第二高度并且包括第二材料的第二源/漏区接触的第二导电插塞。 设置垂直贯穿层间绝缘层与第三源极/漏极区域接触的第三导电插塞，具有第三宽度和第三高度，并且包括第三材料。 第二种材料包括贵金属，贵金属氧化物或钙钛矿型导电氧化物。