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    Mosfet with raised source and drain regions
    4.
    发明授权
    Mosfet with raised source and drain regions 失效
    Mosfet具有升高的源极和漏极区域

    公开(公告)号：US6063676A

    公开(公告)日：2000-05-16

    申请号：US871139

    申请日：1997-06-09

    申请人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

    发明人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768

    CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/41783 ,  H01L21/2257

    摘要： A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.

    摘要翻译： 提供具有表面的表面，表面处的场氧化物区域和表面上方的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层分别在栅极结构和场氧化物区域上方升高第一和第二部分。 掩模层形成在多晶硅层之上，然后被毯式蚀刻以暴露多晶硅层的凸出的第一和第二部分，随后被去除以从多晶硅层形成升高的源极/漏极区。 由于在不使用光刻的情况下制造升高的源极/漏极区域，所以容易制造高密度MOSFET。

    High density MOSFET with raised source and drain regions
    6.
    发明授权
    High density MOSFET with raised source and drain regions 失效
    高密度MOSFET，具有升高的源极和漏极区域

    公开(公告)号：US6043129A

    公开(公告)日：2000-03-28

    申请号：US876540

    申请日：1997-06-09

    申请人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

    发明人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

    IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L27/088

    CPC分类号： H01L29/6659 ,  H01L21/28525 ,  H01L21/76895 ,  H01L27/088 ,  H01L29/41783 ,  H01L21/2257

    摘要： A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the substrate, the polysilicon layer having a raised first portion overlying the gate structure. A masking layer is formed overlying the polysilicon layer and then blanket etched to expose the raised first portion of the polysilicon layer which is subsequently removed. Since the raised first portion of the polysilicon layer is removed without using photolithography, high density MOSFETs are readily fabricated.

    摘要翻译： 提供具有表面，表面处的平坦化场氧化物区域和覆盖表面的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层具有覆盖栅极结构的凸起的第一部分。 形成覆盖多晶硅层的掩模层，然后被毯式蚀刻以暴露随后除去的多晶硅层的凸出的第一部分。 由于在不使用光刻的情况下去除多晶硅层的隆起的第一部分，因此容易制造高密度MOSFET。

    Structure for improving latch-up immunity and interwell isolation in a semiconductor device
    9.
    发明授权
    Structure for improving latch-up immunity and interwell isolation in a semiconductor device 失效
    用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构

    公开(公告)号：US5831313A

    公开(公告)日：1998-11-03

    申请号：US698673

    申请日：1996-08-15

    申请人： Chung-Chyung Han ,  Jeong Yeol Choi ,  Cheun-Der Lien

    发明人： Chung-Chyung Han ,  Jeong Yeol Choi ,  Cheun-Der Lien

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/0921 ,  H01L21/76218 ,  H01L21/823878

    摘要： A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

    摘要翻译： 提供一种用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构。 在一个实施例中，衬底具有形成在其中的上表面和第一掺杂区。 第一掺杂剂区域具有位于衬底的上表面下方的下边界和从衬底的上表面延伸到第一掺杂剂区域的下边界的边界。 具有分别沿着第一掺杂剂区域的下边界和边界定位的第一部分和第二部分的重掺杂区域具有大于第一掺杂剂区域的掺杂剂浓度的基本上均匀的掺杂剂浓度。 重掺杂区域提高了闩锁抗扰度和间隔隔离，而不会降低阈值电压容限。

    Method for fabricating a CMOS device
    10.
    发明授权
    Method for fabricating a CMOS device 失效
    CMOS器件制造方法

    公开(公告)号：US5750424A

    公开(公告)日：1998-05-12

    申请号：US764662

    申请日：1996-12-10

    申请人： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    发明人： Jeong Yeol Choi ,  Chung-Jen Chien ,  Chung-Chyung Han ,  Chuen-Der Lien

    IPC分类号： H01L21/762 ,  H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/76202 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823892

    摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

    摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。