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    Area-efficient power switching cell
    1.
    发明授权
    Area-efficient power switching cell 失效
    区域效率的电力开关电池

    公开(公告)号：US07712066B2

    公开(公告)日：2010-05-04

    申请号：US11322103

    申请日：2005-12-29

    申请人： Martin J. Gasper, Jr. ,  James C. Parker ,  Clayton E. Schneider, Jr.

    发明人： Martin J. Gasper, Jr. ,  James C. Parker ,  Clayton E. Schneider, Jr.

    IPC分类号： G06F9/45 ,  G06F17/50 ,  G06F7/38 ,  H03K19/173

    CPC分类号： H03K17/687

    摘要： A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.

    摘要翻译： 电源开关电路用于至少包括第一电压轨和第二电压轨的集成电路中。 功率开关电路包括至少一个MOS器件，其具有适于连接到第一电压轨的第一源极/漏极，适于连接到第二电压轨的第二源/漏极和适于接收控制信号的栅极。 MOS器件响应于控制信号选择性地将第一电压轨连接到第二电压轨。 第一和第二电压轨形成覆盖功率开关电路的电网，第一和第二电压轨相对于彼此形成在不同的平面中。 电源开关电路和第一电压轨之间的连接在第一和电压轨之间的接口处形成。

    System and method for integrated circuit design and implementation using mixed cell libraries
    2.
    发明授权
    System and method for integrated circuit design and implementation using mixed cell libraries 有权
    使用混合单元库的集成电路设计和实现的系统和方法

    公开(公告)号：US08694940B2

    公开(公告)日：2014-04-08

    申请号：US13546791

    申请日：2012-07-11

    申请人： William R. Griesbach ,  Clayton E. Schneider, Jr.

    发明人： William R. Griesbach ,  Clayton E. Schneider, Jr.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.

    摘要翻译： 一种用于设计诸如集成电路的电路的系统和方法，其允许设计者使用混合单元库。 在一个实施例中，系统包括：（1）细胞放置EDA工具，其被配置为通过将来自混合单元库的单元放入与混合单元库相对应的簇中而将逻辑电路表示转换成物理电路表示，以及（2）互连布线 与细胞放置EDA工具相关联的EDA工具，并配置为在分离簇的缓冲区中路由互连。

    SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DESIGN AND IMPLEMENTATION USING MIXED CELL LIBRARIES
    3.
    发明申请
    SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DESIGN AND IMPLEMENTATION USING MIXED CELL LIBRARIES 有权
    用于集成电路设计和使用混合单元库的实现的系统和方法

    公开(公告)号：US20140019932A1

    公开(公告)日：2014-01-16

    申请号：US13546791

    申请日：2012-07-11

    申请人： William R. Griesbach ,  Clayton E. Schneider, JR.

    发明人： William R. Griesbach ,  Clayton E. Schneider, JR.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.

    摘要翻译： 一种用于设计诸如集成电路的电路的系统和方法，其允许设计者使用混合单元库。 在一个实施例中，系统包括：（1）细胞放置EDA工具，其被配置为通过将来自混合单元库的单元放入与混合单元库相对应的簇中而将逻辑电路表示转换成物理电路表示，以及（2）互连布线 与细胞放置EDA工具相关联的EDA工具，并配置为在分离簇的缓冲区中路由互连。

    Noise rejection Set-Reset Flip-Flop circuitry
    4.
    发明授权
    Noise rejection Set-Reset Flip-Flop circuitry 失效
    降噪设置 - 复位触发器电路

    公开(公告)号：US4506165A

    公开(公告)日：1985-03-19

    申请号：US393764

    申请日：1982-06-30

    申请人： Surender K. Gulati ,  Clayton E. Schneider, Jr.

    发明人： Surender K. Gulati ,  Clayton E. Schneider, Jr.

    IPC分类号： H03K3/037 ,  H03K3/3562 ,  G11C11/40 ,  H03K17/16 ,  H03K17/693

    CPC分类号： H03K3/3562 ,  H03K3/0372

    摘要： Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set and reset terminals which are of the appropriate state at least prior to and during the transition of a clock signal from the low to the high state cause the output terminals of the Flip-Flop to be set to or maintained in preselected levels.

    摘要翻译： 设置复位主从触发器电路使用连接到电路输出端子的反馈电路，并设置和复位输入端子以限制杂散信号的影响，使得只有施加到适当状态的置位和复位端子的信号 至少在从低电平到高电平状态的时钟信号的转换之前和期间，触发器的输出端子被设置为或保持在预选电平。