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1.发明申请公开(公告)号：US20100026378A1
公开(公告)日：2010-02-04
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, JR. , Gregory W. Sheets , Prasad Subbarao
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译： 设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压 缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合 性能目标和（6）在优化目标电压下执行布局的定时签出。
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2.发明授权Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby 有权使用电压调节的集成电路设计方法和由此设计的集成电路公开(公告)号：US08806408B2
公开(公告)日：2014-08-12
申请号：US12364918
申请日：2009-02-03
申请人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
发明人： James C. Parker , Vishwas M. Rao , Clayton E. Schneider, Jr. , Gregory W. Sheets , Prasad Subbarao
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译： 设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压 缩放以实现优化目标电压下的性能目标，如果是，是采用静态电压缩放还是采用自适应电压调整，（5）使用优化目标电压来实现功能IC设计中符合 性能目标和（6）在优化目标电压下执行布局的定时签出。
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公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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4.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US07792234B2
公开(公告)日：2010-09-07
申请号：US11414521
申请日：2006-04-28
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
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公开(公告)号：US07706487B2
公开(公告)日：2010-04-27
申请号：US10964056
申请日：2004-10-12
申请人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
发明人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
IPC分类号： H04B1/10
CPC分类号： G01R31/31715 , H04B3/04 , H04L25/03038 , H04L2025/03356 , H04L2025/03477 , H04L2025/03617
摘要： In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.
摘要翻译： 在训练SERDES时，通过包含发射机，信道和接收机组件的路径发送具有嵌入其中的某些信息位的公共电接口（CEI）训练帧。 本发明分析所得到的接收信号并确定这三个分量的有效总信道脉冲响应。 然后，本发明确定该聚合信道的逆的估计，并且使用该确定来减少已经被引入到已经通过该路径传输的信号中的失真。
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6.发明授权公开(公告)号：US07693088B2
公开(公告)日：2010-04-06
申请号：US11686144
申请日：2007-03-14
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译： 提供了使用数据眼监视器进行数据速率检测的方法和装置。 数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。 通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。 可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。
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7.发明申请公开(公告)号：US20090219978A1
公开(公告)日：2009-09-03
申请号：US12040575
申请日：2008-02-29
IPC分类号： H04B1/38
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one ox more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern. Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译： 为自适应链路伙伴发射机均衡提供了方法和装置。 根据本发明的一个方面，本地收发器通过在所述链路伙伴和所述本地收发器之间的信道上接收训练帧来适配链路伙伴的一个更多的均衡参数，其中所述训练帧由预定的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述预定训练模式是否由所述本地收发器适当地接收来确定所述信道的均衡是否满足一个或多个预定标准。所述预定训练模式可以是诸如PN11模式的伪随机模式。 通道的噪声余量和抖动余量可以任意改进。
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公开(公告)号：US20090110045A1
公开(公告)日：2009-04-30
申请号：US11930780
申请日：2007-10-31
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/0262 , H04L2025/03547
摘要： Methods and apparatus are provided fox equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要翻译： 提供了均衡接收信号的方法和装置。 接收到的信号通过确定接收信号的数据速率来均衡; 获得与所确定的数据速率相关联的一个或多个均衡参数; 以及使用所获得的一个或多个均衡参数来均衡所接收的信号。 均衡参数可以包括例如增益参数，高通滤波器的零控制和在均衡步骤期间使用的一个或多个锁存器的一个或多个阈值设置中的一个或多个，诸如数据锁存器或转换锁存器（或 都）。
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公开(公告)号：US07477849B2
公开(公告)日：2009-01-13
申请号：US10998679
申请日：2004-11-29
IPC分类号： H04B10/02
CPC分类号： H04L25/4908 , H04L27/04 , H04L27/06
摘要： In a communication system comprising first and second nodes, a multilevel amplitude modulated signaling technique is utilized. The first and second nodes may communicate over a Fibre Channel link or other medium. The first and second nodes comprise respective transmitter and receiver pairs, with the transmitter of the first node configured for communication with the receiver of the second node and the receiver of the first node configured for communication with the transmitter of the second node. The first node is configured to generate a signal for transmission over a serial data channel to the second node, the signal having a multilevel amplitude modulated format in which, within a given clock cycle of the signal, multiple bits are represented by a given signal level.
摘要翻译： 在包括第一和第二节点的通信系统中，利用多电平幅度调制信令技术。 第一和第二节点可以通过光纤通道链路或其他介质进行通信。 第一和第二节点包括相应的发射机和接收机对，其中第一节点的发射机被配置用于与第二节点的接收机进行通信，并且第一节点的接收机被配置用于与第二节点的发射机进行通信。 第一节点被配置为生成用于通过串行数据信道传输到第二节点的信号，该信号具有多电平幅度调制格式，其中在信号的给定时钟周期内，多个比特由给定的信号电平 。
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10.发明申请公开(公告)号：US20080191766A1
公开(公告)日：2008-08-14
申请号：US12012758
申请日：2008-02-05
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译： 公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。
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