公开(公告)号：US06787474B2

公开(公告)日：2004-09-07

申请号：US10040378

申请日：2002-01-09

申请人： Daisuke Komada

发明人： Daisuke Komada

IPC分类号： H01L21302

CPC分类号： H01L21/31122 ,  H01L21/76808 ,  H01L21/76816

摘要： The surface of an insulating film made of silicon-containing insulating material is covered with a mask pattern. The insulating film is dry-etched by using the mask pattern as a mask and etching gas which contains C4F8 gas and CxFy gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1). In the dry-etching process, a sufficient etching selection ratio can be obtained between a layer to be etched and an underlying etching stopper film.

摘要翻译： 由含硅绝缘材料制成的绝缘膜的表面被掩模图案覆盖。 通过使用掩模图案作为掩模和包含C 4 F 8气体和C x F y气体（其中x和y是整数并且满足x> = 5且y <=（2x-1））的蚀刻气体来干法蚀刻绝缘膜。 可以在待蚀刻的层和下面的蚀刻停止膜之间获得干蚀刻工艺，足够的蚀刻选择比。

公开(公告)号：US06769819B2

公开(公告)日：2004-08-03

申请号：US09821539

申请日：2001-03-28

申请人： Tsuyoshi Tanaka ,  Daisuke Komada ,  Shiro Yonekura

发明人： Tsuyoshi Tanaka ,  Daisuke Komada ,  Shiro Yonekura

IPC分类号： G02B642

CPC分类号： G02B6/4226 ,  G02B6/4237 ,  G02B6/424 ,  G02B6/4248 ,  G02B6/4251 ,  G02B6/4271

摘要： An optical device module is provided which includes an optical device, an optical fiber an end of which is optically coupled to the optical device, a package containing the optical device and the optical fiber, and an insertion tube fixed air-tightly through the wall of the package, the optical fiber extending through the insertion tube out of the package, wherein the end portion of the optical fiber is offset with respect to the fixed portion, by the insertion tube, of the optical fiber to bend the optical fiber between the end portion and the fixed portion of the optical fiber, then avoiding the displacement of the end of the fiber to be coupled to the optical device due to a change in environment temperatures of the module, and minimize the temperature dependence of device performance. Further, the optical device module may be fabricated such that the end portion of the optical fiber is fixed to a ferrule which is fixed to a ferrule holder which is capable to be deformed plastically, whereby the optical axes of the optical device and the end of the optical fiber can readily be adjusted accurately after assembly.

摘要翻译： 提供了一种光学器件模块，其包括光学器件，光纤，其光端与光学器件光耦合，包含光学器件和光纤的封装以及气密地穿过 所述光纤通过所述插入管从所述封装中延伸，其中所述光纤的端部通过所述光纤的所述插入管相对于所述固定部分偏移以将所述光纤弯曲在所述端部之间 部分和光纤的固定部分，然后避免由于模块的环境温度的变化而耦合到光学装置的光纤的端部的位移，并且最小化器件性能的温度依赖性。 此外，光学器件模块可以被制造成使得光纤的端部固定到固定到能够塑性变形的套圈保持器的套圈，由此光学器件的光轴和端部 组装后光纤可以很容易地精确调整。

公开(公告)号：US06498089B2

公开(公告)日：2002-12-24

申请号：US09955333

申请日：2001-09-19

申请人： Daisuke Komada

发明人： Daisuke Komada

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device, having: a plurality of semiconductor elements formed in a central circuit area of a semiconductor chip; a plurality of insulating layers formed on the semiconductor chip; cavities for forming wiring layers of a multi-layer structure, each of the cavities in each wiring layer having a via hole and a wiring pattern trench; wiring layers of the multi-layer structure including a via conductor filled in the via hole and a wiring pattern filled in the wiring pattern trench; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area in a loop-shape and formed through the insulating layers, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in a corresponding one of the moisture-proof ring trenches. In etching via holes and a moisture-proof ring trench, it is possible to suppress the stopper film in the moisture-proof ring trench from being thinned and to minimize damages to the underlying wiring layer.

公开(公告)号：US5560803A

公开(公告)日：1996-10-01

申请号：US351212

申请日：1994-11-30

申请人： Satoru Mihara ,  Daisuke Komada

发明人： Satoru Mihara ,  Daisuke Komada

IPC分类号： G03F7/42 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H05H1/00 ,  H01L21/00

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： A method for ashing a resist on a wafer in a plasma reaction chamber comprises the steps of flowing a non-activated oxygen containing gas into the plasma reaction chamber immediately before loading the wafer to the plasma reaction chamber, and then carrying out a plasma ashing of the resist. In one of the preferred embodiments, after the reaction chamber was exposed to the atmosphere and then evacuated to vacuum, a mixed gas of oxygen (90% in volume) and water vapor (10% in volume) was flown into the reaction chamber with 1000 seem and 1 Torr for 5 min. and subsequently the ashing was carried out. The method prevents the ashing rate from decreasing with ashing time.

摘要翻译： 在等离子体反应室中在晶片上灰化抗蚀剂的方法包括以下步骤：在将晶片加载到等离子体反应室之前将未活化的含氧气体流入等离子体反应室，然后进行等离子体灰化 抗拒。 在优选实施方案之一中，在将反应室暴露于大气中然后抽真空之后，将氧（体积比为90％）和水蒸汽（体积比为10％）的混合气体以1000 似乎和1乇5分钟。 随后灰化进行。 该方法防止灰化速率随着灰化时间而减少。

公开(公告)号：US20090093379A1

公开(公告)日：2009-04-09

申请号：US11914447

申请日：2006-04-28

申请人： Daisuke Komada

发明人： Daisuke Komada

IPC分类号： C40B50/14 ,  C40B60/14

CPC分类号： B01L3/0248 ,  G01N35/1074 ,  G01N35/109 ,  G01N2035/1037

摘要： The present invention relates to a spot pin (2) including: a liquid holding portion (21) including a tubular portion and defining a liquid holding space (27) for holding a liquid; and an upper limit position definition portion positioned in a middle of the liquid holding portion (21) in an axial direction and defining the upper limit position of the liquid held in the liquid holding portion (21). The upper limit position definition portion has one or a plurality of outside air communication holes (24) communicated with the liquid holding space (27) and opened in the circumferential surface of the liquid holding portion (21).

摘要翻译： 点针（2）技术领域本发明涉及一种点针（2），包括：液体保持部（21），其包括管状部分并限定用于保持液体的液体保持空间（27） 以及位于所述液体保持部（21）的中心位置的上限位置定义部，并且限定保持在所述液体保持部（21）中的液体的上限位置。 上限位置定义部具有与液体保持空间（27）连通且在液体保持部（21）的周面开口的一个或多个外部空气连通孔（24）。

公开(公告)号：US06787907B2

公开(公告)日：2004-09-07

申请号：US09735479

申请日：2000-12-14

申请人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

发明人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76829 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

摘要翻译： 一种半导体器件，具有：在基底的表层中具有导电区域的基底; 覆盖基底表面的绝缘蚀刻阻挡膜; 形成在所述绝缘蚀刻停止膜上的层间绝缘膜; 形成在所述层间绝缘膜中的布线沟槽，所述布线沟槽具有从所述层间绝缘膜的表面的第一深度; 从所述布线沟槽的底表面延伸到所述导电区域的表面的接触孔; 以及嵌入在所述布线沟槽和所述接触孔中的双镶嵌布线层，其中所述层间绝缘膜包括围绕所述布线沟槽的侧壁和底面的第一种绝缘层和具有蚀刻的第二种绝缘层 特性不同于第一种绝缘层。 提供了可以充分保护下面的导电区域并具有高可靠性和小布线电容的双镶嵌布线层的半导体器件。

公开(公告)号：US07119009B2

公开(公告)日：2006-10-10

申请号：US10898938

申请日：2004-07-27

申请人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

发明人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

IPC分类号： H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76829 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

公开(公告)号：US20050001323A1

公开(公告)日：2005-01-06

申请号：US10898938

申请日：2004-07-27

申请人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

发明人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76829 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

摘要翻译： 一种半导体器件，具有：在基底的表层中具有导电区域的基底; 覆盖基底表面的绝缘蚀刻阻挡膜; 形成在所述绝缘蚀刻停止膜上的层间绝缘膜; 形成在所述层间绝缘膜中的布线沟槽，所述布线沟槽具有从所述层间绝缘膜的表面的第一深度; 从所述布线沟槽的底表面延伸到所述导电区域的表面的接触孔; 以及嵌入在所述布线沟槽和所述接触孔中的双镶嵌布线层，其中所述层间绝缘膜包括围绕所述布线沟槽的侧壁和底面的第一种绝缘层和具有蚀刻的第二种绝缘层 特性不同于第一种绝缘层。 提供了可以充分保护下面的导电区域并具有高可靠性和小布线电容的双镶嵌布线层的半导体器件。

公开(公告)号：US06627554B1

公开(公告)日：2003-09-30

申请号：US09537430

申请日：2000-03-27

申请人： Daisuke Komada

发明人： Daisuke Komada

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76832

摘要： A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.

摘要翻译： 具有多层布线结构的半导体器件制造方法包括以下步骤：在半导体衬底上形成绝缘膜，在绝缘膜上形成涂层抗蚀剂，在抗蚀剂中形成布线图形窗口，通过蚀刻绝缘膜形成布线凹槽 通过窗口去除抗蚀剂，通过使用惰性气体将绝缘膜暴露于等离子体气氛，并将金属膜埋入布线凹槽中以形成布线，去除存在于绝缘膜上的反应产物。

公开(公告)号：US06599841B2

公开(公告)日：2003-07-29

申请号：US09342054

申请日：1999-06-29

申请人： Daisuke Komada

发明人： Daisuke Komada

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  H01L21/32136

摘要： A method for fabricating a semiconductor device including a conductive pattern having a first layer including Ti and a second layer including W is presented. The method includes the steps of patterning the conductive pattern by a dry etching and exposing the conductive pattern after the step of the patterning to a plasma containing O, thereby removing the remaining Cl which induces an aftercorrosion problem of the conductive pattern containing the Ti.

摘要翻译： 提出了一种制造半导体器件的方法，该半导体器件包括具有包括Ti的第一层和包括W的第二层的导电图案。 该方法包括以下步骤：通过干蚀刻图案化导电图案，并将图案化步骤之后的导电图案暴露于含有O的等离子体，从而除去残留的Cl，这导致含有Ti的导电图案的后腐蚀问题。