公开(公告)号：US20120242314A1

公开(公告)日：2012-09-27

申请号：US13251343

申请日：2011-10-03

Applicant: Toshimasa Namekawa ,  Daisuke Miyashita ,  Jun Deguchi

Inventor： Toshimasa Namekawa ,  Daisuke Miyashita ,  Jun Deguchi

IPC: G05F1/46

CPC classification number: H03K7/08 ,  H02M3/157

Abstract: A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals.

Abstract translation: DC-DC转换器具有开关元件，低通滤波器，振荡器，AD转换器，误差信号发生器，计数器，比较器，选择器，其被配置为根据以下值来选择多个时钟信号中的一个： 误差信号的下侧位与比较器检测到一致的定时同步;以及切换控制器，被配置为根据由选择器选择的时钟信号来控制开关元件的接通/断开。 选择器选择多个时钟信号中的一个和通过组合包括多个时钟信号中的相邻相位的两个或更多个时钟信号而产生的新的时钟信号。

公开(公告)号：US20120135700A1

公开(公告)日：2012-05-31

申请号：US13369536

申请日：2012-02-09

Applicant: Shouhei KOUSAI ,  Daisuke MIYASHITA ,  Jun DEGUCHI

Inventor： Shouhei KOUSAI ,  Daisuke MIYASHITA ,  Jun DEGUCHI

IPC: H04B1/16 ,  H03K5/04

CPC classification number: H03D7/125

Abstract: A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

Abstract translation: 输出通过混合第一输入信号和第二输入信号而获得的输出信号的频率转换电路具有：输入第一输入信号的第一输入端; 输入第二输入信号的第二输入端; 输出信号输出的输出端子; 具有连接到第一输入端子的第一输入部分和连接到输出端子的输出部分的频率转换元件根据输入到第二输入部分的信号来限制输入到第一输入部分的信号，并输出受限信号 到输出部分; 以及脉冲控制电路，其经由所述第二输入端子接收所述第二输入信号，并将通过将所述第二输入信号的脉冲限制到所述频率转换元件的所述第二输入部分而获得的脉冲信号。

公开(公告)号：US08143933B2

公开(公告)日：2012-03-27

申请号：US12723822

申请日：2010-03-15

Applicant: Jun Deguchi ,  Daisuke Miyashita

Inventor： Jun Deguchi ,  Daisuke Miyashita

IPC: G06G7/12

CPC classification number: H03B19/14

Abstract: A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

Abstract translation: 半导体集成电路包括具有第一单栅极混频器的混频器电路单元，其被配置为接收具有第一频率的第一输入信号和具有第二频率的第二输入信号作为输入;第二单门混频器，被配置为接收第一输入信号 以及从所述第二输入信号的相位反转的相位的第三输入信号作为输入;第三单门混频器，被配置为接收从所述第一输入信号和所述第二输入信号的相位反相的相位的第四输入信号， 配置为接收第三和第四输入信号作为输入的第四单门混频器; 以及1/2分频器单元，被配置为从第一至第四单个栅极混合器接收输出信号作为输入并输出期望的信号。

公开(公告)号：US08135373B2

公开(公告)日：2012-03-13

申请号：US12407957

申请日：2009-03-20

Applicant: Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

Inventor： Jun Deguchi ,  Shouhei Kousai ,  Daisuke Miyashita

IPC: H04B15/00

CPC classification number: H04B1/0053

Abstract: A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

公开(公告)号：US20090253396A1

公开(公告)日：2009-10-08

申请号：US12407957

申请日：2009-03-20

Applicant: Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

Inventor： Jun DEGUCHI ,  Shouhei Kousai ,  Daisuke Miyashita

IPC: H04B1/16 ,  H04B1/06

CPC classification number: H04B1/0053

Abstract: A wireless communication apparatus includes a local oscillator that generates a plurality of LO (Local Oschillation) signals corresponding to frequencies of a plurality of input RF (Radio Frequency) signals, an accumulator that accumulates the plurality of LO signals generated by the local oscillator to generate an accumulated signal, a mixer that mixes the plurality of RF signals and the accumulated signal generated by the accumulator and to generate a plurality of base band signals, and a first signal processing unit that executes a signal process with respect to the plurality of base band signals generated by the mixer.

Abstract translation: 无线通信装置包括本地振荡器，其产生对应于多个输入RF（射频）信号的频率的多个LO（局部烧灼）信号，累加器，其累积由本地振荡器产生的多个LO信号，以产生 累加信号，混合多个RF信号的混频器和由累加器产生的累加信号并产生多个基带信号;以及第一信号处理单元，其对多个基带进行信号处理 由混频器产生的信号。

公开(公告)号：US20090088123A1

公开(公告)日：2009-04-02

申请号：US12240093

申请日：2008-09-29

Applicant: Shouhei Kousai ,  Daisuke Miyashita ,  Jun Deguchi

Inventor： Shouhei Kousai ,  Daisuke Miyashita ,  Jun Deguchi

IPC: H04B1/16 ,  H03D7/00

CPC classification number: H03D7/125

Abstract: A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

Abstract translation: 输出通过混合第一输入信号和第二输入信号而获得的输出信号的频率转换电路具有：输入第一输入信号的第一输入端; 输入第二输入信号的第二输入端; 输出信号输出的输出端子; 具有连接到第一输入端子的第一输入部分和连接到输出端子的输出部分的频率转换元件根据输入到第二输入部分的信号来限制输入到第一输入部分的信号，并输出受限信号 到输出部分; 以及脉冲控制电路，其经由所述第二输入端子接收所述第二输入信号，并将通过将所述第二输入信号的脉冲限制到所述频率转换元件的所述第二输入部分而获得的脉冲信号。

公开(公告)号：US20080303603A1

公开(公告)日：2008-12-11

申请号：US12133589

申请日：2008-06-05

Applicant: Shouhei KOUSAI ,  Daisuke Miyashita

Inventor： Shouhei KOUSAI ,  Daisuke Miyashita

IPC: H03L7/085

CPC classification number: H03L7/099 ,  H03L2207/06

Abstract: A semiconductor integrated circuit device includes a voltage controlled oscillator which controls a bias current or an oscillation frequency to supply an output signal, a phase-locked loop circuit which supplies a frequency control signal based on the output signal supplied from the voltage controlled oscillator, a peak detection circuit which detects a peak of the frequency control signal supplied from the phase-locked loop circuit, and a bias control circuit which produces a bias current based on the peak detected by the peak detection circuit to supply the bias current. The voltage controlled oscillator controls the bias current supplied from the bias control circuit or the oscillation frequency to supply the output signal based on the frequency control signal supplied from the phase-locked loop circuit.

Abstract translation: 半导体集成电路装置包括控制偏置电流或提供输出信号的振荡频率的压控振荡器，基于从压控振荡器提供的输出信号提供频率控制信号的锁相环电路， 峰值检测电路，其检测从锁相环电路提供的频率控制信号的峰值;以及偏置控制电路，其基于由峰值检测电路检测到的峰值产生偏置电流以提供偏置电流。 压控振荡器控制从偏置控制电路提供的偏置电流或振荡频率，以基于从锁相环电路提供的频率控制信号来提供输出信号。

公开(公告)号：US07244009B2

公开(公告)日：2007-07-17

申请号：US11023036

申请日：2004-12-28

Applicant: Atsushi Kobayashi ,  Toshio Kumagai ,  Shuichi Nakano ,  Daisuke Miyashita

Inventor： Atsushi Kobayashi ,  Toshio Kumagai ,  Shuichi Nakano ,  Daisuke Miyashita

IPC: B41J29/38

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17509 ,  B41J2/1752 ,  B41J2/17566

Abstract: Ink type information is read by a read and write system (62) from a semiconductor storage system mounted on ink cartridges (9a to 9d) attached to a cartridge holder (8). A decision control system (61) decides whether or not ink type information has already been stored in ink type storage system (63), and stores the ink type information thus read when the ink type information is not stored. In the case in which the ink cartridge is exchanged, the ink type information is similarly read and it is decided whether or not the same ink type information is identical to the ink type information stored in the ink type storage system (63). If they are not identical to each other, the operation of the recording apparatus is inhibited and a display system (68) is caused to display an error message thereon.

Abstract translation: 墨水类型信息由读取和写入系统（62）从安装在连接到墨盒保持器（8）上的墨盒（9a至9d）上的半导体存储系统读取。 判定控制系统（61）判定墨水类型信息是否已经存储在墨水存储系统（63）中，并且当没有存储墨水类型信息时存储这样读取的墨水类型信息。 在更换墨盒的情况下，类似地读取墨水类型信息，并且确定相同的墨水类型信息是否与存储在墨水存储系统（63）中的墨水类型信息相同。 如果它们不相同，则禁止记录装置的操作，并且使显示系统（68）在其上显示错误消息。

公开(公告)号：US20060152295A1

公开(公告)日：2006-07-13

申请号：US11300367

申请日：2005-12-15

Applicant: Daisuke Miyashita ,  Hiroki Ishikuro

Inventor： Daisuke Miyashita ,  Hiroki Ishikuro

IPC: H03L7/099

CPC classification number: H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor integrated circuit device having a voltage controlled oscillation circuit that is capable of sufficient oscillation performance and a wireless communication device having the semiconductor integrated circuit device are disclosed. A difference between the maximum value and the minimum value of the oscillation output signal is automatically controlled to be substantially equal to the first predetermined voltage which is the threshold voltage of the oscillation MOSFET for sufficient phase noise performance. It is further disclosed that the difference between the maximum value and the minimum value of the oscillation output signal may be varied by the change of the threshold voltage of the MOSFET caused by substrate bias effect, while maintaining the sufficient phase noise performance.

Abstract translation: 公开了一种具有能够具有足够的振荡性能的压控振荡电路和具有半导体集成电路器件的无线通信装置的半导体集成电路器件。 振荡输出信号的最大值和最小值之间的差被自动控制为基本上等于作为用于充分的相位噪声性能的振荡MOSFET的阈值电压的第一预定电压。 进一步公开的是，振荡输出信号的最大值和最小值之间的差异可以通过由衬底偏置效应引起的MOSFET的阈值电压的变化而改变，同时保持足够的相位噪声性能。

公开(公告)号：US20130254632A1

公开(公告)日：2013-09-26

申请号：US13601186

申请日：2012-08-31

Applicant: Daisuke MIYASHITA

Inventor： Daisuke MIYASHITA

IPC: H03M13/13

CPC classification number: G06F11/1008 ,  H03M5/08 ,  H03M13/1117 ,  H03M13/6502 ,  H03M13/6577

Abstract: A decoding device is provided for decoding received data which is coded based on low-density parity-check code. The decoding device includes a variable node operation unit, a check node operation unit, and a circuit in the transmission path between the two units. The variable node operation unit generates secondary probability information based on primary probability information and the coded data. The check node operation unit generates the primary probability information based on the secondary probability information. The circuit transmits the primary probability information and the secondary probability information between the variable node operation unit and the check node operation unit. In addition, at least one of the primary probability information and the secondary probability information transmitted via the transmission path is represented by a time signal.

Abstract translation: 提供了一种解码装置，用于对基于低密度奇偶校验码进行编码的接收数据进行解码。 解码装置包括可变节点操作单元，校验节点操作单元和两个单元之间的传输路径中的电路。 可变节点操作单元基于主概率信息和编码数据生成二次概率信息。 校验节点操作单元基于次要概率信息生成主概率信息。 电路在可变节点运算单元和校验节点运算单元之间传输主要概率信息和次要概率信息。 此外，经由传输路径发送的主要概率信息和次要概率信息中的至少一个由时间信号表示。