公开(公告)号：US08017469B2

公开(公告)日：2011-09-13

申请号：US12357057

申请日：2009-01-21

Applicant: Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

Inventor： Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化物区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

公开(公告)号：US20080274600A1

公开(公告)日：2008-11-06

申请号：US11800204

申请日：2007-05-04

Applicant: Leo Mathew ,  John J. Hackenberg ,  David C. Sing ,  Tab A. Stephens ,  Daniel G. Tekleab ,  Vishal P. Trivedi

Inventor： Leo Mathew ,  John J. Hackenberg ,  David C. Sing ,  Tab A. Stephens ,  Daniel G. Tekleab ,  Vishal P. Trivedi

IPC: H01L21/00

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/66803 ,  H01L29/785

Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).

Abstract translation: 提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213） （b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

公开(公告)号：US20100184260A1

公开(公告)日：2010-07-22

申请号：US12357057

申请日：2009-01-21

Applicant: Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

Inventor： Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

IPC: H01L21/82 ,  H01L21/77 ,  H01L21/04 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化物区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

公开(公告)号：US08258035B2

公开(公告)日：2012-09-04

申请号：US11800204

申请日：2007-05-04

Applicant: Leo Mathew ,  John J. Hackenberg ,  David C. Sing ,  Tab A. Stephens ,  Daniel G. Tekleab ,  Vishal P. Trivedi

Inventor： Leo Mathew ,  John J. Hackenberg ,  David C. Sing ,  Tab A. Stephens ,  Daniel G. Tekleab ,  Vishal P. Trivedi

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/66803 ,  H01L29/785

Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).

Abstract translation: 提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213） （b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

公开(公告)号：US20100109044A1

公开(公告)日：2010-05-06

申请号：US12261589

申请日：2008-10-30

Applicant: Daniel G. Tekleab ,  Srikanth B. Samavedam

Inventor： Daniel G. Tekleab ,  Srikanth B. Samavedam

IPC: H01L29/778 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

Abstract: A semiconductor process and apparatus includes forming PMOS transistors (72) with enhanced hole mobility in the channel region by epitaxially growing a bi-axially stressed forward graded silicon germanium channel region layer (22) and a counter-doped silicon cap layer (23) prior to forming a PMOS gate structure (34) and associated source/drain regions (38, 40) in the channel region layer(s).

Abstract translation: 一种半导体工艺和装置包括通过外延生长双轴向应变前向梯度硅锗沟道区域层（22）和反掺杂硅覆盖层（23），在沟道区域中形成具有增强的空穴迁移率的PMOS晶体管（72） 以在沟道区域层中形成PMOS栅极结构（34）和相关联的源极/漏极区域（38,40）。