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    Method for forming a deposited oxide layer
    1.
    发明授权
    Method for forming a deposited oxide layer 有权
    形成沉积氧化物层的方法

    公开(公告)号：US07767588B2

    公开(公告)日：2010-08-03

    申请号：US11364128

    申请日：2006-02-28

    Applicant: Tien Ying Luo ,  Rajesh A. Rao

    Inventor： Tien Ying Luo ,  Rajesh A. Rao

    IPC: H01L21/31 ,  H01L21/461

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    Abstract: An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.

    Abstract translation: 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。

    Multilayer silicon nitride deposition for a semiconductor device
    2.
    发明申请
    Multilayer silicon nitride deposition for a semiconductor device 审中-公开
    用于半导体器件的多层氮化硅沉积

    公开(公告)号：US20080173908A1

    公开(公告)日：2008-07-24

    申请号：US11655461

    申请日：2007-01-19

    Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/8238

    CPC classification number: H01L21/02348 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

    Abstract translation: 提供了制造半导体器件的方法，其包括（a）提供配备有栅极和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（131），所述第一应力源材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（133），所述第二应力源材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

    Method of making a high quality thin dielectric layer
    4.
    发明授权
    Method of making a high quality thin dielectric layer 有权
    制造高品质薄介电层的方法

    公开(公告)号：US07001852B2

    公开(公告)日：2006-02-21

    申请号：US10836149

    申请日：2004-04-30

    Applicant: Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

    Inventor： Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

    IPC: H01L21/31

    CPC classification number: H01L21/02255 ,  H01L21/02299 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/513

    Abstract: A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density. The second anneal causes a second density and thickness change in the base oxide layer from the first thickness and density to a second thickness and density. The second thickness is larger than the first thickness and the second density is on the order of the greater than or equal to the first density.

    Abstract translation: 制造高品质薄介电层的方法包括在第一环境中的第一温度下对衬底和覆盖在衬底的顶表面上的基底氧化物层进行退火，并在第二环境中的第二温度退火衬底和基底氧化物层 在第一退火之后。 第一环境包括选自氮，氩和氦环境的惰性气体环境。 在第一退火之前，基底氧化物层具有初始厚度和初始密度。 第一次退火使基底氧化物层中的初始密度和厚度变化从初始厚度和密度到第一厚度和密度，而不会在基底氧化物层内引入环境的氮，氩或氦。 第一厚度小于初始厚度，第一密度大于初始密度。 第二退火导致基础氧化物层中的第二密度和厚度从第一厚度和密度变化到第二厚度和密度。 第二厚度大于第一厚度，第二密度大于或等于第一密度。

    Dual high-K oxides with SiGe channel
    5.
    再颁专利
    Dual high-K oxides with SiGe channel 有权
    具有SiGe通道的双高K氧化物

    公开(公告)号：USRE45955E1

    公开(公告)日：2016-03-29

    申请号：US14452736

    申请日：2014-08-06

    Applicant: Tien Ying Luo ,  Gauri V. Karve ,  Daniel K. Tekleab

    Inventor： Tien Ying Luo ,  Gauri V. Karve ,  Daniel K. Tekleab

    IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

    CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

    Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

    Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

    MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE
    7.
    发明申请
    MULTILAYER SILICON NITRIDE DEPOSITION FOR A SEMICONDUCTOR DEVICE 审中-公开
    用于半导体器件的多层硅氮化物沉积

    公开(公告)号：US20110210401A1

    公开(公告)日：2011-09-01

    申请号：US12713262

    申请日：2010-02-26

    Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

    IPC: H01L27/092 ,  H01L29/78

    CPC classification number: H01L21/823807 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02274 ,  H01L27/092 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

    Abstract translation: 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

    METHOD OF REMOVING DEFECTS FROM A DIELECTRIC MATERIAL IN A SEMICONDUCTOR
    9.
    发明申请
    METHOD OF REMOVING DEFECTS FROM A DIELECTRIC MATERIAL IN A SEMICONDUCTOR 有权
    从半导体中的介电材料中去除缺陷的方法

    公开(公告)号：US20090075434A1

    公开(公告)日：2009-03-19

    申请号：US11855557

    申请日：2007-09-14

    Applicant: Kurt H. Junker ,  Tien-Ying Luo ,  Dina H. Triyoso

    Inventor： Kurt H. Junker ,  Tien-Ying Luo ,  Dina H. Triyoso

    IPC: H01L21/30

    CPC classification number: H01L21/3105 ,  H01L21/2686 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28273 ,  H01L21/3003 ,  H01L28/40 ,  H01L29/517

    Abstract: A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N2/D2), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.

    Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成高介电常数材料，在高介电常数材料上形成导电材料，并使用紫外线辐射在非氧化环境中进行退火以去除高电介质中的缺陷 恒定材料。 非氧化性环境的实例包括例如氮，氘，氘代形成气体（N 2 / D 2），氦气，氩气或这些中的任何两种或更多种的组合。 可以进行使用紫外线辐射的附加退火。 这些额外的退火可能发生在非氧化或氧化环境中。

    Dual high-k oxides with sige channel
    10.
    发明授权
    Dual high-k oxides with sige channel 有权
    双通道高K氧化物

    公开(公告)号：US08017469B2

    公开(公告)日：2011-09-13

    申请号：US12357057

    申请日：2009-01-21

    Applicant: Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

    Inventor： Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

    IPC: H01L21/8238

    CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

    Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

    Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化物区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

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