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公开(公告)号：US20140284716A1
公开(公告)日：2014-09-25
申请号：US14302174
申请日：2014-06-11
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并且具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中具有第二导电性的第一阱区域 类型，并且其中在操作期间在栅极结构下形成沟道区，以及与第一阱区相邻的具有第二导电类型并且具有比第一阱区更高的掺杂剂浓度的第二阱区，以建立路径 以承载第二导电类型的电荷载体，远离包含沟道区和源极区之间的结的寄生双极晶体管。
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公开(公告)号：US09123804B2
公开(公告)日：2015-09-01
申请号：US14302174
申请日：2014-06-11
IPC分类号： H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并且具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中具有第二导电性的第一阱区域 类型，并且其中在操作期间在栅极结构下形成沟道区，以及与第一阱区相邻的具有第二导电类型并且具有比第一阱区更高的掺杂剂浓度的第二阱区，以建立路径 以承载第二导电类型的电荷载体，远离包含沟道区和源极区之间的结的寄生双极晶体管。
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公开(公告)号：US08772870B2
公开(公告)日：2014-07-08
申请号：US13665665
申请日：2012-10-31
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中的阱区，具有第二导电类型 并且其中在操作期间在栅极结构下方形成沟道区，以及与半导体衬底中的阱区相邻并具有第二导电类型的分流区。 并联区具有比阱区更高的掺杂浓度，以建立用于将阱区电耦合到源区的电位的第二导电类型的载流子的分流路径。
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公开(公告)号：US20140117446A1
公开(公告)日：2014-05-01
申请号：US13665665
申请日：2012-10-31
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中的阱区，具有第二导电类型 并且其中在操作期间在栅极结构下方形成沟道区，以及与半导体衬底中的阱区相邻并具有第二导电类型的分流区。 并联区具有比阱区更高的掺杂浓度，以建立用于将阱区电耦合到源区的电位的第二导电类型的载流子的分流路径。
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公开(公告)号：US08134241B2
公开(公告)日：2012-03-13
申请号：US13179295
申请日：2011-07-08
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译： 在共同衬底上具有有源器件区域和焊盘（BP）区域的电子元件期望地包括位于BP之下的电介质区域，以在电子元件被缩放到更高功率和/或操作时降低BP的寄生阻抗及其互连 频率。 由平原（例如，仅氧化物）电介质区域产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有比它们被嵌入和/或更靠近衬底TEC的介电材料的热膨胀系数小的热膨胀系数（TEC）的电隔离夹杂物的复合电介质区域来避免。 对于硅衬底，聚硅或非晶硅适用于介电材料的夹杂物和氧化硅。 夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。
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公开(公告)号：US20100140814A1
公开(公告)日：2010-06-10
申请号：US12328319
申请日：2008-12-04
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L21/768 , H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译： 具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少 作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。 由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有电绝缘的包含物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。 对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。 夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。
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公开(公告)号：US20110266687A1
公开(公告)日：2011-11-03
申请号：US13179295
申请日：2011-07-08
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.
摘要翻译： 在共同衬底上具有有源器件区域和焊盘（BP）区域的电子元件期望地包括位于BP之下的电介质区域，以在电子元件被缩放到更高功率和/或操作时降低BP的寄生阻抗及其互连 频率。 由平原（例如，仅氧化物）电介质区域产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有比它们被嵌入和/或更靠近衬底TEC的介电材料的热膨胀系数小的热膨胀系数（TEC）的电隔离夹杂物的复合电介质区域来避免。 对于硅衬底，聚硅或非晶硅适用于介电材料的夹杂物和氧化硅。 夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。
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8.发明授权公开(公告)号：US07998852B2
公开(公告)日：2011-08-16
申请号：US12328319
申请日：2008-12-04
申请人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
发明人： Jeffrey K. Jones , Margaret A. Szymanowski , Michele L. Miera , Xiaowei Ren , Wayne R. Burger , Mark A. Bennett , Colin Kerr
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L29/0649 , H01L2224/05076 , H01L2224/05558 , H01L2224/05576 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/05042 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).
摘要翻译： 具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少 作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。 由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有电绝缘夹杂物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。 对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。 夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。
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