公开(公告)号：US20140284716A1

公开(公告)日：2014-09-25

申请号：US14302174

申请日：2014-06-11

申请人： Xiaowei Ren ,  David C. Burdeaux ,  Robert P. Davidson ,  Michele L. Miera

发明人： Xiaowei Ren ,  David C. Burdeaux ,  Robert P. Davidson ,  Michele L. Miera

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7835 ,  Y02E10/50

摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并且具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中具有第二导电性的第一阱区域 类型，并且其中在操作期间在栅极结构下形成沟道区，以及与第一阱区相邻的具有第二导电类型并且具有比第一阱区更高的掺杂剂浓度的第二阱区，以建立路径 以承载第二导电类型的电荷载体，远离包含沟道区和源极区之间的结的寄生双极晶体管。

公开(公告)号：US20140159198A1

公开(公告)日：2014-06-12

申请号：US13712051

申请日：2012-12-12

申请人： XIAOWEI REN ,  WAYNE R. BURGER

发明人： XIAOWEI REN ,  WAYNE R. BURGER

IPC分类号： H01L49/02

CPC分类号： H01L23/5223 ,  H01L28/75 ,  H01L28/84 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.

摘要翻译： 集成无源器件（例如，金属绝缘体金属或MIM，电容器）的实施例及其形成方法包括在半导体衬底（例如，在衬底表面上方的电介质层上）沉积复合电极，以及将绝缘体层沉积在 复合电极。 复合电极包括底层电极和沉积在下面电极的顶表面上的上覆电极。 底层电极由第一导电材料（例如，AlCuW）形成，并且上覆电极由第二不同的导电材料（例如AlCu）形成。 底层电极的顶表面可能具有相对粗糙的表面形态，并且上覆电极的顶表面可具有相对平滑的表面形态。 对于高频，高功率应用，复合电极和绝缘体层可能比一些传统的集成无源器件更厚。

公开(公告)号：US20100140814A1

公开(公告)日：2010-06-10

申请号：US12328319

申请日：2008-12-04

申请人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

发明人： Jeffrey K. Jones ,  Margaret A. Szymanowski ,  Michele L. Miera ,  Xiaowei Ren ,  Wayne R. Burger ,  Mark A. Bennett ,  Colin Kerr

IPC分类号： H01L21/768 ,  H01L23/488

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L29/0649 ,  H01L2224/05076 ,  H01L2224/05558 ,  H01L2224/05576 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).

摘要翻译： 具有在公共衬底（45）上的有源器件区（46）和焊盘（BP）区（60）的电子元件（44,44'，44“）理想地包括位于BP（35）下方的电介质区域，以减少 作为电子元件（44,44'，44“）的BP（35）及其互连（41）的寄生阻抗被缩放到更高的功率和/或工作频率。 由平坦（例如，仅氧化物）介电区域（36'）产生的机械应力可能不利地影响性能，制造产量，焊盘到设备的接近度和占用面积。 这可以通过提供具有电绝缘的包含物（65,65'，65'）的复合电介质区域（65,65'，65'）来避免，所述电绝缘夹杂物的热膨胀系数（TEC）小于电介质材料（78， 78'，78“），其中它们被嵌入和/或更靠近衬底（45）TEC。 对于硅衬底（45），多晶硅或非晶硅适合用于介电材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。 夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

公开(公告)号：US07508021B2

公开(公告)日：2009-03-24

申请号：US11760775

申请日：2007-06-10

申请人： Xiaowei Ren ,  Daniel J. Lamey

发明人： Xiaowei Ren ,  Daniel J. Lamey

IPC分类号： H01L27/108

CPC分类号： H01L27/0629 ,  H01L23/5225 ,  H01L23/642 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/60 ,  H01L29/41758 ,  H01L29/94 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (62); and a metallization feature (70) disposed about and isolated from at least two sides of the top plate (62), the metallization feature (70) for coupling the bottom plate (86,88) to the shield (74). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

摘要翻译： 集成分流电容器包括底板（86,88），覆盖在底板的一部分上的电容器电介质（92），覆盖电容器电介质的顶板（62），覆盖顶部的一部分的屏蔽（74） 板（62）; 以及金属化特征（70），其设置在所述顶板（62）的至少两侧周围并与所述顶板隔离，所述金属化特征（70）用于将所述底板（86,88）联接到所述屏蔽件（74）。 在一个实施例中，RF功率晶体管具有包括本文所述的集成分流电容器的阻抗匹配网络。

公开(公告)号：US20070297120A1

公开(公告)日：2007-12-27

申请号：US11760775

申请日：2007-06-10

申请人： Xiaowei Ren ,  Daniel J. Lamey

发明人： Xiaowei Ren ,  Daniel J. Lamey

IPC分类号： H01G4/228

CPC分类号： H01L27/0629 ,  H01L23/5225 ,  H01L23/642 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/60 ,  H01L29/41758 ,  H01L29/94 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated shunt capacitor comprises a bottom plate (62), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (64) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate; and a metallization feature (70) disposed about and isolated from at least two sides of the top plate, the metallization feature for coupling the bottom plate to the shield. In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

摘要翻译： 集成分流电容器包括底板（62），覆盖在底板的一部分上的电容器电介质（92），覆盖电容器电介质的顶板（64），覆盖顶板的一部分的屏蔽层（74） 以及金属化特征（70），其设置在所述顶板的至少两侧的周围并且与所述顶板的至少两侧隔离，所述金属化特征用于将所述底板耦合到所述屏蔽。 在一个实施例中，RF功率晶体管具有包括本文所述的集成分流电容器的阻抗匹配网络。

公开(公告)号：US08753948B2

公开(公告)日：2014-06-17

申请号：US13285557

申请日：2011-10-31

申请人： Xiaowei Ren ,  Robert P. Davidson ,  Mark A. Detar

发明人： Xiaowei Ren ,  Robert P. Davidson ,  Mark A. Detar

IPC分类号： H01L21/331

CPC分类号： H01L29/0878 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.

摘要翻译： 提供横向扩散的金属氧化物半导体（LDMOS）晶体管。 LDMOS晶体管包括具有源极区，沟道区和漏极区的衬底。 第一植入物形成在衬底中的第一深度。 在源极区域和漏极区域之间的衬底的沟道区域上形成栅电极。 在基板的源极区域中形成第二植入物; 第二植入体在栅电极下方以预定距离横向扩散。 第三植入物形成在衬底的漏极区域中的第二深度; 第二深度小于第一深度。 还提供了一种用于形成LDMOS晶体管的方法。

公开(公告)号：US20100140714A1

公开(公告)日：2010-06-10

申请号：US12328325

申请日：2008-12-04

申请人： Xiaowei Ren ,  Wayne R. Burger ,  Colin Kerr ,  Mark A. Bennett

发明人： Xiaowei Ren ,  Wayne R. Burger ,  Colin Kerr ,  Mark A. Bennett

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L27/00

CPC分类号： H01L27/08 ,  H01L21/763 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/10

摘要： Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).

摘要翻译： 在共用衬底（45）上具有有源器件区域（46）和集成无源器件（IPD）区域（60）的电子元件（44,44'，44“）优选地包括复合电介质区域（62,62'，62 “）在IPD（IP）（35）下方的IPD区域中以减少耦合到衬底（45）的电磁（EM）（33）。 可以通过在复合介电区域（62,62'）中提供电隔离的夹杂物（65,65'，65“）来避免由平坦介电区域（36'）产生的机械应力及其对性能，制造产量和占用面积的有害影响， ，62“）具有比所述复合介电区域（62,62'，62”）中的电介质材料（78,78'，78“）的热膨胀系数小的热膨胀系数（TEC）的材料。 对于硅衬底（45），非单晶硅适用于电介质材料（78,78'，78“）的夹杂物（65,65'，65”）和氧化硅。 夹杂物（65,65'，65“）优选具有由电介质材料（78,78'，78”）分隔开并封闭在其中的刀片形状。

公开(公告)号：US07368668B2

公开(公告)日：2008-05-06

申请号：US11347461

申请日：2006-02-03

申请人： Xiaowei Ren ,  Robert A. Pryor ,  Daniel J. Lamey

发明人： Xiaowei Ren ,  Robert A. Pryor ,  Daniel J. Lamey

IPC分类号： H05K9/00

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41758 ,  H01L2223/6611 ,  H01L2224/48 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

摘要翻译： 诸如RF LDMOS的半导体器件，具有具有一对堆叠金属层的接地屏蔽。 第一金属层沿着半导体器件的长度延伸并且形成在半导体器件本体的上表面上。 第一层具有一系列规则间隔开的横向第一槽。 与第一金属层共同延伸并位于第二金属层上方的第二金属层具有一系列规则间隔开的横向第二槽。 第二槽覆盖在第一槽之间的空间中，并且第二金属层的连续部分覆盖在第一槽上。 这些槽基本上平行于在接地屏蔽上延伸的导线。 接地屏蔽不仅限于两个金属层。 接地屏蔽具有重复的单元设计，便于自动设计。

公开(公告)号：US09064712B2

公开(公告)日：2015-06-23

申请号：US12855479

申请日：2010-08-12

申请人： Paul W. Sanders ,  Wayne R. Burger ,  Thuy B. Dao ,  Joel E. Keys ,  Michael F. Petras ,  Robert A. Pryor ,  Xiaowei Ren

发明人： Paul W. Sanders ,  Wayne R. Burger ,  Thuy B. Dao ,  Joel E. Keys ,  Michael F. Petras ,  Robert A. Pryor ,  Xiaowei Ren

IPC分类号： H01L23/522 ,  H01L27/06 ,  H01L23/48 ,  H01L23/66 ,  H03F3/195 ,  H01L23/00

CPC分类号： H01L23/66 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0727 ,  H01L28/10 ,  H01L28/40 ,  H01L29/7816 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30107 ,  H03F3/195 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.

摘要翻译： 使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q， ）用于IC（46）。 这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。 有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。 平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。 晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等） （41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69） 使用贯通衬底通孔（98,98'）来最小化寄生电阻。 通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。 其结果是先前无法获得的单片微波IC（46,58）。

公开(公告)号：US08283748B2

公开(公告)日：2012-10-09

申请号：US13277847

申请日：2011-10-20

申请人： Xiaowei Ren ,  Wayne R. Burger ,  Colin Kerr ,  Mark A. Bennett

发明人： Xiaowei Ren ,  Wayne R. Burger ,  Colin Kerr ,  Mark A. Bennett

IPC分类号： H01L21/70

CPC分类号： H01L27/08 ,  H01L21/763 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/10

摘要： Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

摘要翻译： 具有有源器件区域和在公共衬底上的集成无源器件（IPD）区域的电子元件优选地包括在IPD下面的IPD区域中的复合电介质区域，以减少与衬底的电磁（E-M）耦合。 通过在具有小于介电材料的热膨胀系数（TEC）的材料的复合介电区域中提供电隔离的夹杂物，可以避免由平坦介质区域产生的机械应力及其对性能，制造产量和占用面积的有害影响 在复合电介质区域中。 对于硅衬底，非单晶硅适用于介电材料的夹杂物和氧化硅。 夹杂物优选具有由介电材料分离并封闭在电介质材料内的刀片状形状。