公开(公告)号：US5844425A

公开(公告)日：1998-12-01

申请号：US694712

申请日：1996-07-19

申请人： Hung T. Nguyen ,  Chit Ah Mak ,  Steve W. T. Liu

发明人： Hung T. Nguyen ,  Chit Ah Mak ,  Steve W. T. Liu

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00315

摘要： An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.

摘要翻译： 具有过压耐受性的三态输出缓冲器，能够承受三次过电压而不产生反向电流或闭锁，输出缓冲器具有稳定的保护电路，用于将P沟道驱动晶体管的N阱和栅极驱动到输出焊盘电压 输出焊盘电压过大。 稳定保护电路包括用于控制偏置N阱的开关晶体管的滞后电路。 滞后电路的存在使得保护电路具有输入滞后特性，因此当三态输出缓冲器电源电压接近输出焊盘电压时，防止了N阱偏置晶体管的过度切换。

公开(公告)号：US06680626B2

公开(公告)日：2004-01-20

申请号：US10161931

申请日：2002-06-05

申请人： Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

发明人： Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

IPC分类号： H03K522

CPC分类号： H03K5/2481

摘要： A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

摘要翻译： 具有一对交叉耦合信号调理装置的差分接收器改善了转换时间和数据信号完整性。 在一个实施例中，差分接收器包括两个信号输入节点和多个晶体管以及两个信号输出节点。 一对交叉耦合的信号调节装置耦合到晶体管并且用于减小两个输出节点之间的电压摆幅，从而将晶体管保持在饱和区域。

公开(公告)号：US20090140808A1

公开(公告)日：2009-06-04

申请号：US11947085

申请日：2007-11-29

申请人： Chit Ah MAK ,  Chun Fai WONG ,  Lap Chi LEUNG ,  Xiaofei KUANG ,  Jennifer Shuet Yan HO ,  David Kwok Kuen KWONG

发明人： Chit Ah MAK ,  Chun Fai WONG ,  Lap Chi LEUNG ,  Xiaofei KUANG ,  Jennifer Shuet Yan HO ,  David Kwok Kuen KWONG

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F1/486 ,  H03F1/56 ,  H03F3/45192 ,  H03F2200/36 ,  H03F2200/513 ,  H03F2203/45138 ,  H03F2203/45356 ,  H03G1/0023 ,  H03G7/004 ,  H03G7/06

摘要： A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

摘要翻译： 一种增益控制电路，包括具有第一端子和第二端子的电阻器; 运算放大器，其反相端电耦合到所述电阻器的所述第一端子; 其非反相端子; 及其输出端子; 放大器电路，用于将所述运算放大器输出的电压变化变换成基本指数的电流变化; 其中所述放大器电路的输出电耦合到所述运算放大器的所述反相端。 上述增益控制电路能够在低电压和低功率条件下以线性方式执行宽带宽输入信号缓冲。 该电路还提供低输出阻抗，而不需要额外的缓冲器，因此最小化电路尺寸和制造成本。

公开(公告)号：US5559477A

公开(公告)日：1996-09-24

申请号：US528603

申请日：1995-09-15

申请人： Orhan Tozun ,  Chit-Ah Mak ,  Werner Hoeft

发明人： Orhan Tozun ,  Chit-Ah Mak ,  Werner Hoeft

IPC分类号： H03K3/03 ,  H03K5/156 ,  H03L7/099 ,  H03B5/02 ,  H03K3/017

CPC分类号： H03L7/0805 ,  H03K3/0315 ,  H03K5/1565 ,  H03L7/0995

摘要： Five CMOS inverters are connected in a series ring to form an oscillator. Current to the inverters is controlled to establish gate delays of the inverters and thereby determine a frequency of oscillation of the oscillator. The oscillator is included in a phase locked loop where the gate delay of the inverters is selected by selecting the value of a frequency divider of the phase locked loop. The selected delay is used to form a train of pulses with a desired duty cycle.

摘要翻译： 五个CMOS反相器串联连接成一个振荡器。 控制到逆变器的电流以建立反相器的门延迟，从而确定振荡器的振荡频率。 振荡器包括在锁相环中，通过选择锁相环的分频器的值来选择反相器的栅极延迟。 选择的延迟用于形成具有所需占空比的脉冲序列。

公开(公告)号：US07659780B2

公开(公告)日：2010-02-09

申请号：US11947085

申请日：2007-11-29

申请人： Chit Ah Mak ,  Chun Fai Wong ,  Lap Chi Leung ,  Xiaofei Kuang ,  Jennifer Shuet Yan Ho ,  David Kwok Kuen Kwong

发明人： Chit Ah Mak ,  Chun Fai Wong ,  Lap Chi Leung ,  Xiaofei Kuang ,  Jennifer Shuet Yan Ho ,  David Kwok Kuen Kwong

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F1/486 ,  H03F1/56 ,  H03F3/45192 ,  H03F2200/36 ,  H03F2200/513 ,  H03F2203/45138 ,  H03F2203/45356 ,  H03G1/0023 ,  H03G7/004 ,  H03G7/06

摘要： A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

摘要翻译： 一种增益控制电路，包括具有第一端子和第二端子的电阻器; 运算放大器，其反相端电耦合到所述电阻器的所述第一端子; 其非反相端子; 及其输出端子; 放大器电路，用于将所述运算放大器输出的电压变化变换成基本指数的电流变化; 其中所述放大器电路的输出电耦合到所述运算放大器的所述反相端。 上述增益控制电路能够在低电压和低功率条件下以线性度执行宽带宽输入信号缓冲。 该电路还提供低输出阻抗，而不需要额外的缓冲器，因此最小化电路尺寸和制造成本。