公开(公告)号：US06274909B1

公开(公告)日：2001-08-14

申请号：US09434562

申请日：1999-11-12

Applicant: Kun-Zen Chang ,  Deng-Shun Chang ,  Rong-Tai Kao

Inventor： Kun-Zen Chang ,  Deng-Shun Chang ,  Rong-Tai Kao

IPC: H01L2972

CPC classification number: H01L27/0251 ,  Y10S438/983

Abstract: In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.

Abstract translation: 在本发明中，围绕包含ESD装置或电路的区域产生深N型壁。 ESD器件或电路连接到芯片焊盘，并且首先被P +保护环包围。 P +保护环然后被深N型墙包围，以阻止ESD事件或电压过冲的过电流到达内部电路。 深N型壁包括位于深N阱顶部的N阱内的N +扩散。 深N型壁的高度约为4至6微米，这提供了从ESD事件或电压过冲吸收大部分电流的能力。

公开(公告)号：US5674761A

公开(公告)日：1997-10-07

申请号：US641768

申请日：1996-05-02

Applicant: Kun-Zen Chang ,  Ching-Yuan Lin

Inventor： Kun-Zen Chang ,  Ching-Yuan Lin

IPC: H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0266

Abstract: A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a specific conductivity type, also used for the heavily doped source and drain regions of attached FET devices. After photoresist processing, used to mask the attached FET devices, a second ion implantation step, opposite in conductivity type then the first implant, is used to complete the ESD protection diode, for the ESD protection device. This large area diode reduces junction breakdown voltage, while allowing ESD current to be discharged more efficiently then for smaller ESD protection counterparts.

Abstract translation: 已经开发了一种用于形成具有降低的结击穿电压，同时形成包含FET器件的集成电路的ESD保护器件的方法。 本发明的特征在于通过使用特定导电类型的第一离子注入步骤形成大面积的ESD保护二极管，其也用于连接的FET器件的重掺杂源极和漏极区域。 在光致抗蚀剂处理之后，用于掩蔽所附加的FET器件，第二离子注入步骤用于完成用于ESD保护器件的ESD保护二极管。 这种大面积二极管可以降低结击穿电压，同时可以更有效地放电ESD电流，从而降低ESD保护对等体。

公开(公告)号：US5275872A

公开(公告)日：1994-01-04

申请号：US742412

申请日：1991-08-08

Applicant: Kun-Zen Chang

Inventor： Kun-Zen Chang

IPC: H01L21/321 ,  H01L21/336 ,  H01L29/786 ,  B32B17/00

CPC classification number: H01L29/66757 ,  H01L21/321 ,  H01L29/78675 ,  Y10S148/15 ,  Y10S428/901 ,  Y10T428/24926 ,  Y10T428/265

Abstract: An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.

Abstract translation: 一种在多晶硅层中具有源极区，漏极区和沟道区的改进的场效应晶体管，其改进在于，多晶硅层具有近似相同浓度的体现在其中的N和P型掺杂剂，其用于抑制 P / N路口。

公开(公告)号：US6097641A

公开(公告)日：2000-08-01

申请号：US431132

申请日：1999-11-01

Applicant: Nicky C. Lu ,  Kun-Zen Chang

Inventor： Nicky C. Lu ,  Kun-Zen Chang

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  G11C16/04

CPC classification number: H01L27/10873 ,  H01L27/105 ,  H01L27/1052

Abstract: A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

公开(公告)号：US6009023A

公开(公告)日：1999-12-28

申请号：US84409

申请日：1998-05-26

Applicant: Nicky C. Lu ,  Kun-Zen Chang

Inventor： Nicky C. Lu ,  Kun-Zen Chang

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  G11C7/00

CPC classification number: H01L27/10873 ,  H01L27/105 ,  H01L27/1052

Abstract: A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

公开(公告)号：US06107134A

公开(公告)日：2000-08-22

申请号：US431134

申请日：1999-11-01

Applicant: Nicky C. Lu ,  Kun-Zen Chang

Inventor： Nicky C. Lu ,  Kun-Zen Chang

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105

CPC classification number: H01L27/10873 ,  H01L27/105 ,  H01L27/1052

Abstract: A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

Abstract translation: 描述了具有改善的外围电路性能的DRAM装置。 通过选择性地具有在其栅电极施加较低电压的外围电路中具有较薄栅极氧化物的MOS晶体管来提高性能。 DRAM器件将通过在存储器单元中具有较厚栅极氧化物的MOS晶体管以及在其栅电极处受到较高电压的选定外围电路来保持可靠性。 此外，本发明描述了制造具有选择性地放置多个栅极氧化物厚度的DRAM器件的方法。

公开(公告)号：US5789784A

公开(公告)日：1998-08-04

申请号：US844687

申请日：1997-04-21

Applicant: Kun-Zen Chang ,  Ching-Yuan Lin

Inventor： Kun-Zen Chang ,  Ching-Yuan Lin

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0266

Abstract: A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a specific conductivity type, also used for the heavily doped source and drain regions of attached FET devices. After photoresist processing, used to mask the attached FET devices, a second ion implantation step, opposite in conductivity type then the first implant, is used to complete the ESD protection diode, for the ESD protection device. This large area diode reduces junction breakdown voltage, while allowing ESD current to be discharged more efficiently then for smaller ESD protection counterparts.

Abstract translation: 已经开发了一种用于形成具有降低的结击穿电压，同时形成包含FET器件的集成电路的ESD保护器件的方法。 本发明的特征在于通过使用特定导电类型的第一离子注入步骤形成大面积的ESD保护二极管，其也用于连接的FET器件的重掺杂源极和漏极区域。 在光致抗蚀剂处理之后，用于掩蔽所附加的FET器件，第二离子注入步骤用于完成用于ESD保护器件的ESD保护二极管。 这种大面积二极管可以降低结击穿电压，同时可以更有效地放电ESD电流，从而降低ESD保护对等体。

公开(公告)号：US5064775A

公开(公告)日：1991-11-12

申请号：US577156

申请日：1990-09-04

Applicant: Kun-Zen Chang

Inventor： Kun-Zen Chang

IPC: H01L21/321 ,  H01L21/336 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L21/321 ,  H01L29/78675 ,  Y10S148/15 ,  Y10S428/901 ,  Y10T428/24926 ,  Y10T428/265

Abstract: A process of fabricating an improved transistor on a polycrystalline silicon layer, wherein N and P type dopants, in approximate equal concentrations, are introduced into the layer, and the layer heated. The resultant modified polycrystalline silicon layer inhibits the migration of dopants, used to form the active regions of the device, during subsequent heating steps. An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.

Abstract translation: 在多晶硅层上制造改进的晶体管的方法，其中将近似相等浓度的N和P型掺杂剂引入层中，并且加热该层。 所产生的改性多晶硅层在随后的加热步骤期间抑制用于形成器件的有源区的掺杂剂的迁移。 一种在多晶硅层中具有源极区，漏极区和沟道区的改进的场效应晶体管，其改进在于，多晶硅层具有近似相同浓度的体现在其中的N和P型掺杂剂，其用于抑制 P / N路口。

公开(公告)号：US5243234A

公开(公告)日：1993-09-07

申请号：US673973

申请日：1991-03-20

Applicant: Ming-Zen Lin ,  Kun-Zen Chang ,  Jyh-Chyurn Guo

Inventor： Ming-Zen Lin ,  Kun-Zen Chang ,  Jyh-Chyurn Guo

IPC: H01L29/78 ,  H03K17/06 ,  H03K17/081

CPC classification number: H01L29/7816 ,  H01L29/7801 ,  H01L29/7831 ,  H03K17/063 ,  H03K17/08104

Abstract: A double polysilicon dual gate LDMOSFET structure combined with a detecting circuit can be used to reduce the ON state resistance and without degradation of the breakdown voltage of the LDMOSFET. In the ON state, a drift region is driven into accumulation. In the OFF state, a gate is made to float and thereby avoid degradation of the breakdown voltage. A switch or transistor is modulated to either allow applied voltage to bias the gate for enabling the drift region to be driven into accumulation or to cause the gate to float to prevent the driving of the drift region by the voltage.

Abstract translation: 结合检测电路的双重多晶硅双栅极LDMOSFET结构可用于降低导通状态电阻并且不降低LDMOSFET的击穿电压。 在ON状态下，漂移区被驱动成积累。 在OFF状态下，使栅极浮动，从而避免击穿电压的劣化。 调制开关或晶体管以允许施加的电压偏置栅极，以使漂移区域能够被驱动成积聚或使栅极浮动以防止漂移区域被电压驱动。