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公开(公告)号：US06792508B1
公开(公告)日：2004-09-14
申请号：US09591656
申请日：2000-06-09
IPC分类号： G06F1208
CPC分类号： G06F12/0802 , G06F12/0862 , G06F12/0864 , G06F12/0895 , G06F2212/1016 , G06F2212/2515
摘要： A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译： 用于处理设备的高速缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM组高速缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。 寄存器（32）定义主存储器（20）的连续块的起始地址。 与RAM组相关联的数据阵列（38）可以逐行地填充，因为处理核心要求线路，或者填充数据阵列（38）时的起始地址为 加载到寄存器（32）中。 由于从处理核心命中漏错逻辑（46）接收到地址，起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）用于确定是否 数据存在于RAM集合中，或者数据是否必须从主存储器（20）加载。 命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。
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公开(公告)号：US06606687B1
公开(公告)日：2003-08-12
申请号：US09447194
申请日：1999-11-22
IPC分类号： G06F1200
CPC分类号： G06F12/0804
摘要： A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function, the MAX counter (82) counts downward while cache entries at the address given by the MAX counter (82) are written to main memory (16) if the entry is marked as dirty. If an interrupt occurs, the MAX counter is disabled until a subsequent clean request is issued after the interrupt is serviced.
摘要翻译： VIVT（虚拟索引，虚拟标签）缓存（18）使用可中断的硬件清理功能来清除上下文切换期间高速缓存中的脏条目。 MAX计数器（82）和MIN寄存器（84）定义了脏的高速缓存位置的范围。 在硬件清理功能期间，如果条目被标记为脏，则MAX计数器（82）向下计数，而由MAX计数器（82）给出的地址处的缓存条目被写入主存储器（16）。 如果发生中断，则在中断服务完成之后，MAX计数器将被禁止，直到发出后续清除请求。
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公开(公告)号：US07386671B2
公开(公告)日：2008-06-10
申请号：US10891821
申请日：2004-07-14
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0864
摘要： A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译： 用于处理设备的高速缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM组高速缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。 寄存器（32）定义主存储器（20）的连续块的起始地址。 与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上 地址被加载到寄存器（32）中。 由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定 数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。 命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。
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公开(公告)号：US06826652B1
公开(公告)日：2004-11-30
申请号：US09591537
申请日：2000-06-09
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F2212/2515
摘要： A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译： 用于处理的缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM集缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。 寄存器（32）定义主存储器（20）的连续块的起始地址。 与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上 地址被加载到寄存器（32）中。 由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定 数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。 命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。
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5.发明授权Unified memory management system for multi processor heterogeneous architecture 有权用于多处理器异构架构的统一内存管理系统公开(公告)号：US07509391B1
公开(公告)日：2009-03-24
申请号：US09448569
申请日：1999-11-23
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F12/1027 , G06F12/1081
摘要： A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual address space mapped to an external shared memory (20). The MMUs (19, 32) may perform the translation between a virtual address and the physical address associated with the external shared memory (20). Access to the shared memory (20) is controlled using a unified memory management system.
摘要翻译： 多处理器系统8包括多个处理设备，包括DSP（10），处理器单元（MPU）（21），协处理器（30）和DMA通道（31）。 一些设备可以包括允许设备（10,21,30,31）与映射到外部共享存储器（20）的大的虚拟地址空间一起工作的内部MMU（19,32）。 MMU（19,32）可以执行虚拟地址与与外部共享存储器（20）相关联的物理地址之间的转换。 使用统一的存储器管理系统来控制对共享存储器（20）的访问。
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6.发明授权公开(公告)号：US07111177B1
公开(公告)日：2006-09-19
申请号：US09696052
申请日：2000-10-25
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/329 , G06F9/4893 , Y02D10/16 , Y02D10/24
摘要： A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list.
摘要翻译： 分布式处理系统（10）包括多个处理模块，例如MPU（12），DSP（14）和协处理器/ DMA通道（16）。 电力管理软件（38）结合用于各种处理模块的简档（36）和执行的任务被用于构建满足预定功率目标的场景，例如在封装热约束内提供最大操作或使用最小能量。 在操作过程中监视与任务相关的实际活动，以确保与目标的兼容性。 可以动态地改变任务的分配，以适应环境条件的变化和任务列表的变化。
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