公开(公告)号：US07573739B2

公开(公告)日：2009-08-11

申请号：US11713770

申请日：2007-03-02

申请人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim ,  Donggun Park

发明人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim ,  Donggun Park

IPC分类号： G11C11/34

CPC分类号： G11C11/50 ,  G11C11/56 ,  G11C16/0475 ,  G11C23/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a memory device and a method of forming the same, in one embodiment, the memory device comprises a substrate and a bit line on the substrate extending in a first direction. A first word line structure is provided on the bit line and spaced apart from, and insulated from, the bit line, the first word line structure extending in a second direction transverse to the first direction. An electrode is coupled to the bit line extending over the first word line structure and spaced apart from the first word line structure by a first gap. A second word line structure is over the electrode and spaced apart from the electrode by a second gap, the second word line structure extending in the second direction. The electrode is cantilevered between the first word line structure and the second word line structure such that the electrode deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.

摘要翻译： 在存储器件及其形成方法中，在一个实施例中，存储器件包括衬底和在第一方向上延伸的衬底上的位线。 第一字线结构设置在位线上并且与位线隔开并绝缘，第一字线结构在横向于第一方向的第二方向上延伸。 电极耦合到在第一字线结构上延伸并且与第一字线结构隔开第一间隙的位线。 第二字线结构在电极之上并且与电极间隔开第二间隙，第二字线结构沿第二方向延伸。 电极在第一字线结构和第二字线结构之间是悬臂的，使得电极在第一弯曲位置通过第一间隙偏转以与第一字线结构的顶部电耦合，并且偏转以电耦合 第二字线结构的底部在第二弯曲位置通过第二间隙，并且在静止位置与第一字线结构和第二字线结构隔离。

公开(公告)号：US20050285204A1

公开(公告)日：2005-12-29

申请号：US11033526

申请日：2005-01-12

申请人： Sungmin Kim ,  Donggun Park ,  Eunjung Yoon ,  Semyeong Jang ,  Keunnam Kim ,  Yongchul Oh

发明人： Sungmin Kim ,  Donggun Park ,  Eunjung Yoon ,  Semyeong Jang ,  Keunnam Kim ,  Yongchul Oh

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684

摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括具有单元区域和外围电路区域的半导体衬底，单元区域中的半导体衬底的一部分和包括隔离区域的外围电路区域 限定有源区，所述有源区的一部分突出于所述隔离区的上表面之上，以限定至少两个有源沟道;在所述半导体衬底的有源区上形成的包括所述至少两个突出的有源沟道的栅介质层， 形成在栅极电介质层和半导体衬底的隔离区域上的栅极电极，以及形成在栅电极两侧的半导体衬底的有源区域中的源极/漏极区域。

公开(公告)号：US07394116B2

公开(公告)日：2008-07-01

申请号：US11033526

申请日：2005-01-12

申请人： Sungmin Kim ,  Donggun Park ,  Eunjung Yoon ,  Semyeong Jang ,  Keunnam Kim ,  Yongchul Oh

发明人： Sungmin Kim ,  Donggun Park ,  Eunjung Yoon ,  Semyeong Jang ,  Keunnam Kim ,  Yongchul Oh

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684

摘要： In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括具有单元区域和外围电路区域的半导体衬底，单元区域中的半导体衬底的一部分和包括隔离区域的外围电路区域 限定有源区，所述有源区的一部分突出于所述隔离区的上表面之上，以限定至少两个有源沟道;在所述半导体衬底的有源区上形成的包括所述至少两个突出的有源沟道的栅介质层， 形成在栅极电介质层和半导体衬底的隔离区域上的栅极电极，以及形成在栅电极两侧的半导体衬底的有源区域中的源极/漏极区域。

公开(公告)号：US20120039691A1

公开(公告)日：2012-02-16

申请号：US13208032

申请日：2011-08-11

申请人： KISANG KIM ,  Taehyuk Ahn ,  Donggun Park ,  Sangwoun Lee ,  Bongsun Kim

发明人： KISANG KIM ,  Taehyuk Ahn ,  Donggun Park ,  Sangwoun Lee ,  Bongsun Kim

IPC分类号： B65G49/00

CPC分类号： B65G47/71 ,  B65G47/642

摘要： The present inventive concept provides a substrate treating system. The substrate treating system has a plurality of process facilities and at least one buffer station. Each of the process facilities respectively includes a transfer module in which a transfer robot is provided and a treating module connected to the transfer module. A buffer station is located between each of adjacent transfer modules. The buffer stations are provided to transfer substrates between the transfer modules. The plurality of process facilities includes a first facility in which the treating module is located on a first side of an imaginary connection line provided along a direction in which the transfer modules and the buffer stations are arranged and a second facility in which the treating module is located on a second side of the imaginary connection line. The transfer module of the first facility further protrudes toward the first side of the imaginary connection line farther than the transfer module of the second facility.

摘要翻译： 本发明构思提供了一种基板处理系统。 衬底处理系统具有多个处理设备和至少一个缓冲站。 每个处理设备分别包括其中设置有传送机器人的传送模块和连接到传送模块的处理模块。 缓冲站位于每个相邻的传输模块之间。 提供缓冲站以在传送模块之间传送衬底。 多个处理设备包括第一设备，其中处理模块位于沿着传送模块和缓冲站布置的方向设置的虚拟连接线的第一侧，以及第二设备，处理模块 位于虚拟连接线的第二侧。 第一设施的传送模块进一步向虚拟连接线的第一侧突出，比第二设施的传送模块更远。

公开(公告)号：US20070267676A1

公开(公告)日：2007-11-22

申请号：US11714161

申请日：2007-03-06

申请人： Keunnam Kim ,  Makoto Yoshida ,  Donggun Park ,  Wounsuck Yang

发明人： Keunnam Kim ,  Makoto Yoshida ,  Donggun Park ,  Wounsuck Yang

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L29/7851 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10861 ,  H01L29/66621 ,  H01L29/66795

摘要： Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including at least one buried gate structure, buried entirely below an upper surface of an active fin and an upper surface of the isolation region.

摘要翻译： 示例性实施例涉及一种形成场效应晶体管（FET）和场效应晶体管（FET）的方法，场效应晶体管（FET）包括至少一个掩埋栅极结构，其完全埋在有源鳍片的上表面下方，隔离区域的上表面 。

公开(公告)号：US20080048246A1

公开(公告)日：2008-02-28

申请号：US11713770

申请日：2007-03-02

申请人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim ,  Donggun Park

发明人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim ,  Donggun Park

IPC分类号： H01L29/792

CPC分类号： G11C11/50 ,  G11C11/56 ,  G11C16/0475 ,  G11C23/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a memory device and a method of forming the same, in one embodiment, the memory device comprises a substrate and a bit line on the substrate extending in a first direction. A first word line structure is provided on the bit line and spaced apart from, and insulated from, the bit line, the first word line structure extending in a second direction transverse to the first direction. An electrode is coupled to the bit line extending over the first word line structure and spaced apart from the first word line structure by a first gap. A second word line structure is over the electrode and spaced apart from the electrode by a second gap, the second word line structure extending in the second direction. The electrode is cantilevered between the first word line structure and the second word line structure such that the electrode deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.

摘要翻译： 在存储器件及其形成方法中，在一个实施例中，存储器件包括衬底和在第一方向上延伸的衬底上的位线。 第一字线结构设置在位线上并且与位线隔开并绝缘，第一字线结构在横向于第一方向的第二方向上延伸。 电极耦合到在第一字线结构上延伸并且与第一字线结构隔开第一间隙的位线。 第二字线结构在电极之上并且与电极间隔开第二间隙，第二字线结构沿第二方向延伸。 电极在第一字线结构和第二字线结构之间是悬臂的，使得电极在第一弯曲位置通过第一间隙偏转以与第一字线结构的顶部电耦合，并且偏转以电耦合 第二字线结构的底部在第二弯曲位置通过第二间隙，并且在静止位置与第一字线结构和第二字线结构隔离。

公开(公告)号：US6005409A

公开(公告)日：1999-12-21

申请号：US657485

申请日：1996-06-04

申请人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

发明人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/12

摘要： A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage. In another embodiment, a method for monitoring damage in unprotected plurality of transistors during wafer fabrication includes performing a test sequence including applying a constant voltage of a predetermined voltage level for a predetermined period of time, and utilizing the test sequence in-line with the wafer fabrication. In addition, detecting damage further includes programmably controlling the steps of performing and utilizing during wafer fabrication, wherein programmably controlling is performed with a computer system.

摘要翻译： 一种用于检测多个晶体管中的损伤的方法，包括测量多个晶体管的至少一个特性，施加预定电压电平的恒定电压达预定时间段，并且重新测量多个晶体管的至少一个特性 的晶体管，其中所述至少一个特性的变化指示对所述多个晶体管的损坏。 在一个方面，预定电压电平为约9MV / cm，预定时间段为约1秒。 在另一方面，测量至少一个特性包括测量阈值电压，并且至少一个特性的变化包括阈值电压的偏移。 在另一个实施例中，一种用于在晶片制造期间监测未受保护的多个晶体管的损坏的方法包括执行测试序列，包括在预定时间段内施加预定电压电平的恒定电压，并且利用与晶片成一直线的测试序列 制造。 此外，检测损伤进一步包括可编程地控制在晶片制造期间执行和利用的步骤，其中可用计算机系统执行可编程控制。