公开(公告)号：US6005409A

公开(公告)日：1999-12-21

申请号：US657485

申请日：1996-06-04

申请人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

发明人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/12

摘要： A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage. In another embodiment, a method for monitoring damage in unprotected plurality of transistors during wafer fabrication includes performing a test sequence including applying a constant voltage of a predetermined voltage level for a predetermined period of time, and utilizing the test sequence in-line with the wafer fabrication. In addition, detecting damage further includes programmably controlling the steps of performing and utilizing during wafer fabrication, wherein programmably controlling is performed with a computer system.

摘要翻译： 一种用于检测多个晶体管中的损伤的方法，包括测量多个晶体管的至少一个特性，施加预定电压电平的恒定电压达预定时间段，并且重新测量多个晶体管的至少一个特性 的晶体管，其中所述至少一个特性的变化指示对所述多个晶体管的损坏。 在一个方面，预定电压电平为约9MV / cm，预定时间段为约1秒。 在另一方面，测量至少一个特性包括测量阈值电压，并且至少一个特性的变化包括阈值电压的偏移。 在另一个实施例中，一种用于在晶片制造期间监测未受保护的多个晶体管的损坏的方法包括执行测试序列，包括在预定时间段内施加预定电压电平的恒定电压，并且利用与晶片成一直线的测试序列 制造。 此外，检测损伤进一步包括可编程地控制在晶片制造期间执行和利用的步骤，其中可用计算机系统执行可编程控制。

公开(公告)号：US08790970B2

公开(公告)日：2014-07-29

申请号：US11446697

申请日：2006-06-05

申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

公开(公告)号：US07892901B2

公开(公告)日：2011-02-22

申请号：US11604161

申请日：2006-11-25

申请人： Yee-Chia Yeo ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76289 ,  H01L21/84

摘要： A silicon-on-insulator semiconductor device which includes a substrate; an insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for fabricating the silicon-on-insulator semiconductor device is further disclosed.

摘要翻译： 一种绝缘体上硅半导体器件，包括：衬底; 覆盖衬底的绝缘体层; 多个跨越绝缘体层的应变硅岛，应变硅岛通过台面隔离相互隔离; 以及形成在应变硅岛上的多个晶体管。 进一步公开了一种制造绝缘体上硅半导体器件的方法。

公开(公告)号：US07745279B2

公开(公告)日：2010-06-29

申请号：US11331703

申请日：2006-01-13

申请人： Yee-Chia Yeo ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L21/8242

CPC分类号： H01L27/0805 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/65 ,  H01L29/66181 ,  H01L29/94 ,  Y10S257/905 ,  Y10S257/908

摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

摘要翻译： 在包括硅表面层的半导体衬底上形成去耦电容器。 在半导体表面层的一部分中形成基本平坦的底部电极。 电容器电介质覆盖在底部电极上。 电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。 在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

公开(公告)号：US20090155965A1

公开(公告)日：2009-06-18

申请号：US12391307

申请日：2009-02-24

申请人： Horng-Huei Tseng ,  Jhy-Chyum Guo ,  Chenming Hu ,  Da-Chi Lin

发明人： Horng-Huei Tseng ,  Jhy-Chyum Guo ,  Chenming Hu ,  Da-Chi Lin

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L29/7842 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxide region.

摘要翻译： 提供了一种方法，其包括在半导体衬底上形成第一半导体层，在第一半导体层上生长第二半导体层，在第一半导体层上形成复合形状，每个复合形状包括上覆氧化物形状和基底 第二半导体形状，第一半导体层的部分暴露在复合形状之间，在复合形状的侧面上形成间隔物，在第一半导体层的暴露的顶部形成掩埋的氧化硅区域，并且在第一半导体层的部分位置 潜在的第二半导体形状，选择性地去除导致第二半导体形状的耐氧化形状和间隔物，以及形成第二半导体形状的半导体器件，其中半导体器件的第一部分覆盖第一半导体层，并且其中第二部分 半导体器件叠加 y是一个埋置的氧化硅区域。

公开(公告)号：US07372107B2

公开(公告)日：2008-05-13

申请号：US11207681

申请日：2005-08-19

申请人： Yee-Chia Yeo ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/84

摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric layer can overlie the recess-resistant layer. A semiconductor layer overlying the buried insulator stack. Active devices, such as transistors and diodes, can be formed in the semiconductor layer.

摘要翻译： 绝缘体上半导体结构包括衬底和覆盖衬底的掩埋绝缘体堆叠。 掩埋绝缘体堆叠包括覆盖第一介电层的第一介电层和凹陷层。 第二电介质层可以覆盖在耐凹陷层上。 覆盖埋层绝缘体叠层的半导体层。 可以在半导体层中形成有源器件，例如晶体管和二极管。

公开(公告)号：US07357838B2

公开(公告)日：2008-04-15

申请号：US11074738

申请日：2005-03-08

申请人： Chun Chieh Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

发明人： Chun Chieh Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

IPC分类号： C30B23/00

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.

摘要翻译： 提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

公开(公告)号：US07319258B2

公开(公告)日：2008-01-15

申请号：US10901763

申请日：2004-07-28

申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Hung-Wei Chen ,  Tim Tsao ,  Chenming Hu

发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Hung-Wei Chen ,  Tim Tsao ,  Chenming Hu

IPC分类号： H01L21/01 ,  H01L21/12

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/78654

摘要： A semiconductor-on-insulator device includes a silicon active layer with a crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a crystal direction. Transistors oriented on a direction are formed on the silicon active layer.

摘要翻译： 绝缘体上半导体器件包括布置在绝缘体层上的具有<100>晶体方向的硅有源层。 将绝缘体层放置在具有<110>晶体方向的衬底上。 在硅有源层上形成沿<100>方向取向的晶体管。

公开(公告)号：US20070111454A1

公开(公告)日：2007-05-17

申请号：US11649453

申请日：2007-01-03

申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

公开(公告)号：US07214991B2

公开(公告)日：2007-05-08

申请号：US10313887

申请日：2002-12-06

申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L29/76

CPC分类号： H01L27/1211 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to the output terminal, and a gate electrode; and an input terminal connected to the gate electrodes of the first and second multiple-gate transistors. Each of the first and second multiple-gate transistors may further include a semiconductor fin formed vertically on an insulating layer on top of a substrate, a gate dielectric layer overlying the semiconductor fin, and a gate electrode wrapping around the semiconductor fin separating the source and drain regions.

摘要翻译： 一种逆变器，包括：第一多栅极晶体管，其包括连接到电源的源极，连接到输出端子的漏极和栅极电极; 第二多栅极晶体管，其包括连接到地的源极，连接到输出端子的漏极和栅极电极; 以及连接到第一和第二多栅极晶体管的栅电极的输入端子。 第一和第二多栅极晶体管中的每一个还可以包括在衬底顶部的绝缘层上垂直形成的半导体鳍片，覆盖在半导体鳍片上的栅极电介质层，以及围绕分离源极的半导体鳍状物包围的栅电极，以及 漏区。