公开(公告)号：US5612627A

公开(公告)日：1997-03-18

申请号：US348645

申请日：1994-12-01

申请人： Nguyen D. Bui ,  John T. Yue ,  Van Pham

发明人： Nguyen D. Bui ,  John T. Yue ,  Van Pham

IPC分类号： G01R27/26 ,  G01R31/28

CPC分类号： G01R31/2853 ,  G01R31/2858

摘要： A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

摘要翻译： 通过具有阻挡层的互连结构在第一方向上进行基本恒定的电流，以确定结构在第一电流方向上的寿命。 通过基本相同的互连结构在第二方向上进行基本上相同的电流，以确定结构在第二电流方向上的寿命。 对相同的结构重复这些测试，但具有不同的阻挡层厚度。 比较这些寿命测试的结果以确定阻挡层对结构中电迁移的影响，可用于设计阻挡层以优化结构的寿命和速度。

公开(公告)号：US6005409A

公开(公告)日：1999-12-21

申请号：US657485

申请日：1996-06-04

申请人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

发明人： Nguyen D. Bui ,  Chenming Hu ,  Donggun Park ,  Scott Zheng

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/12

摘要： A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage. In another embodiment, a method for monitoring damage in unprotected plurality of transistors during wafer fabrication includes performing a test sequence including applying a constant voltage of a predetermined voltage level for a predetermined period of time, and utilizing the test sequence in-line with the wafer fabrication. In addition, detecting damage further includes programmably controlling the steps of performing and utilizing during wafer fabrication, wherein programmably controlling is performed with a computer system.

摘要翻译： 一种用于检测多个晶体管中的损伤的方法，包括测量多个晶体管的至少一个特性，施加预定电压电平的恒定电压达预定时间段，并且重新测量多个晶体管的至少一个特性 的晶体管，其中所述至少一个特性的变化指示对所述多个晶体管的损坏。 在一个方面，预定电压电平为约9MV / cm，预定时间段为约1秒。 在另一方面，测量至少一个特性包括测量阈值电压，并且至少一个特性的变化包括阈值电压的偏移。 在另一个实施例中，一种用于在晶片制造期间监测未受保护的多个晶体管的损坏的方法包括执行测试序列，包括在预定时间段内施加预定电压电平的恒定电压，并且利用与晶片成一直线的测试序列 制造。 此外，检测损伤进一步包括可编程地控制在晶片制造期间执行和利用的步骤，其中可用计算机系统执行可编程控制。

公开(公告)号：US06472233B1

公开(公告)日：2002-10-29

申请号：US09586960

申请日：2000-06-05

申请人： Khaled Z. Ahmed ,  Nguyen D. Bui ,  Effiong Ibok ,  John R. Hauser

发明人： Khaled Z. Ahmed ,  Nguyen D. Bui ,  Effiong Ibok ,  John R. Hauser

IPC分类号： G01R3126

CPC分类号： H01L22/34 ,  G01R31/2621 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

摘要翻译： 一种用于在强反转中从C-V分析中提取多晶硅栅极掺杂的设备和方法，特别是对于超薄栅极氧化物。 对于次20埃氧化物MOS器件，沟道长度小于约10微米的晶体管并联连接，以避免强反转中的外在电容滚降。 使用端子电容的传输线模型来估计通道长度的上限，这是模拟栅隧道电流和有限通道电阻的不可忽略的因素。

公开(公告)号：US5966024A

公开(公告)日：1999-10-12

申请号：US784325

申请日：1997-01-16

申请人： Nguyen D. Bui ,  Scott Zheng

发明人： Nguyen D. Bui ,  Scott Zheng

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L23/544

CPC分类号： G01R31/2621 ,  B24B37/013 ,  H01L22/26 ,  H01L22/34 ,  H01L22/12 ,  H01L2924/0002

摘要： Techniques for measuring process induced damage, such as damage experienced during plasma etching or ion implementation, utilize a differential amplifier having multi-layer antennas (capacitors) of different sizes formed on respective inputs. Measurement of .DELTA.Ids (the difference between Ids.sub.1 and Ids.sub.2 off a MOSFET of the differential pair) or .DELTA.Idlin provides a sensitive and accurate measure of process induced damage. The techniques can be applied to monitor process induced damage while the manufacturing process is ongoing or as a measure of quality of the finished product.

摘要翻译： 用于测量过程诱导的损伤的技术，例如在等离子体蚀刻或离子实施期间经历的损坏，利用形成在相应输入上的具有不同尺寸的多层天线（电容器）的差分放大器。 DELTA Ids的测量（差分对的MOSFET之间的Ids1和Ids2之间的差异）或DELTA Idlin提供了对过程引起的损伤的敏感和准确的测量。 这些技术可以用于在制造过程正在进行时监测过程引起的损坏，或者作为成品质量的度量。

公开(公告)号：US5598009A

公开(公告)日：1997-01-28

申请号：US468222

申请日：1995-06-06

申请人： Nguyen D. Bui

发明人： Nguyen D. Bui

IPC分类号： H01L21/3213 ,  H01L23/485 ,  H01L23/58

CPC分类号： H01L24/05 ,  H01L21/32137 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05599 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074

摘要： An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number. In practice, the ratio R would be chosen to be a minimum so that deleterious plasma currents attracted to the gate area would be reduced. In a particular implementation, the transistor includes plural gates each having a layer of at least partially conductive material of area A.sub.gn where n is any integer between 1 and N and where N is the total number of gates. In this case, the plural gates are interconnected and the ratio R is a predetermined number equal to A.sub.p /A.sub.gtotal, where A.sub.gtotal is the sum of the areas A.sub.gn and n is any integer between 1 and N. The novel method for testing multiple gate transistors includes the steps of connecting a first terminal of each of said transistors to a ground; interconnecting a second terminal of each transistor and applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.

摘要翻译： 改进的晶体管设计及其构造和测试方法相同。 新颖的晶体管设计方法包括提供具有多个公共栅极区域的晶体管的步骤; 将每个门区连接到垫; 并且调整焊盘的面积与栅极区域的总和的比率以提供预定的比率。 可以通过在单个栅极实现中调整栅极的尺寸或者调整多栅极配置中的栅极的数量来调节该比率。 新型晶体管包括衬底，设置在衬底上的至少一个源极; 设置在所述基板上的至少一个漏极; 以及设置在源极和漏极之间的衬底上的至少一个栅极。 栅极具有连接到区域Ap的焊盘的区域Ag的至少部分导电材料的第一层。 根据本教导，焊盘Ap的面积与栅极Ag的面积的天线比率R是预定数量。 在实践中，比率R将被选择为最小值，使得吸引到栅极区域的有害等离子体电流将被减小。 在具体实施方式中，晶体管包括多个栅极，每个栅极具有区域Agn的至少部分导电材料的层，其中n是1和N之间的任何整数，其中N是门的总数。 在这种情况下，多个栅极互连，比率R是等于Ap / Agtotal的预定数量，其中Agtotal是区域Agn之和，n是1与N之间的任何整数。用于测试多个栅极晶体管的新颖方法 包括将每个所述晶体管的第一端子连接到地的步骤; 互连每个晶体管的第二端子并施加第一电源电位; 以及选择性地将第二电源电位施加到所选晶体管的第三端。

公开(公告)号：US6100101A

公开(公告)日：2000-08-08

申请号：US179172

申请日：1998-10-27

申请人： Amit P. Marathe ,  Nguyen D. Bui ,  Van Pham

发明人： Amit P. Marathe ,  Nguyen D. Bui ,  Van Pham

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  Y10S148/162

摘要： A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

摘要翻译： 基于空隙尺寸的特定半导体晶片的分类从经历等温测试的晶片获得的西格马数据和T0.1％的故障数据获得。 将特定晶片的西格玛数据和T0.1％故障数据与存储的数据相比较，存储数据对应于多个空白类别中的每一个的西格玛和T0.1％数据的范围，并且特定晶片基于存储的 数据。 基于T50％故障数据和σ值计算T0.1％故障数据，从而可以利用小的样本量来获取存储的数据。

公开(公告)号：US06320391B1

公开(公告)日：2001-11-20

申请号：US09076219

申请日：1998-05-08

申请人： Nguyen D. Bui

发明人： Nguyen D. Bui

IPC分类号： G01N2720

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： An interconnection test structure for evaluating more accurately and reliably electromigration characteristics is provided. The test structure includes an elongated metal test conductor having a first end and a second end, small extension metal conductors connected to the first end and the second end of the test conductor, and a plurality of vias disposed in the small extension metal conductors adjacent the first end and the second end of the test conductor. As a result, the current density of the plurality of vias is made to be less than the current density of the test conductor.

摘要翻译： 提供了用于评估更准确和可靠的电迁移特性的互连测试结构。 测试结构包括具有第一端和第二端的细长金属测试导体，连接到测试导体的第一端和第二端的小的延伸金属导体，以及设置在与小型延伸金属导体相邻的多个通孔中 测试导体的第一端和第二端。 结果，使多个通孔的电流密度小于测试导体的电流密度。