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1.发明授权System and method for terminating lock-step sequences in a multiprocessor system 失效用于在多处理器系统中终止锁步序列的系统和方法公开(公告)号：US06754787B2
公开(公告)日：2004-06-22
申请号：US10302372
申请日：2002-11-22
IPC分类号： G06F1200
CPC分类号： G06F11/0793 , G06F9/52 , G06F11/0724 , G06F13/1663
摘要： There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.
摘要翻译： 提供了一种用于包含耦合到主存储器的多个处理器的处理系统中的控制电路，用于扰乱从处理器接收到的锁步骤序列的存储器请求。 控制电路包括存储器请求发生器，用于产生至少一个可操作以终止锁定步骤序列的存储器请求的存储器请求。
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2.发明授权System and method for improved transfer of data between multiple processors and I/O bridges 失效用于改善多处理器和I / O桥之间的数据传输的系统和方法
公开(公告)号：US06128677A
公开(公告)日：2000-10-03
申请号：US943677
申请日：1997-10-15
CPC分类号： G06F13/4031
摘要： A controller is provided, for use in a processing system containing a plurality of processors operable to communicate with a plurality of I/O devices, for directing a first I/O request issued by a first selected one of the plurality of processors to a targeted one of the I/O devices. The controller device comprises a counter for counting a number of retries associated with the first I/O request and comparison circuitry for comparing a count value in the counter with a first predetermined limit, wherein the controller, in response to a determination that the count value in the counter exceeds the first predetermined limit, blocks all other I/O requests issued by the plurality of processors from being directed to the targeted I/O device.
摘要翻译： 提供控制器，用于包含可操作以与多个I / O设备进行通信的多个处理器的处理系统，用于将由多个处理器中的第一选定的处理器发出的第一I / O请求引导到目标 其中一个I / O设备。 控制器装置包括用于计数与第一I / O请求相关联的重试次数的计数器和用于将计数器中的计数值与第一预定极限进行比较的比较电路，其中控制器响应于确定计数值 在计数器中超过第一预定限制，阻止由多个处理器发出的所有其它I / O请求被引导到目标I / O设备。
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3.发明授权
公开(公告)号：US6073216A
公开(公告)日：2000-06-06
申请号：US980882
申请日：1997-11-25
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0817 , G06F11/1064
摘要： There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.
摘要翻译： 公开了一种用于处理系统中的存储器控制电路，该处理系统包含通过公共总线耦合到主存储器的多个处理器。 存储器控制电路适于根据所选择的一致性算法在处理系统中实现基于目录的一致性，并且包括：1）监视电路，用于检测与主存储器相关联的一致性目录中的一致性损坏; 以及2）相干性控制电路，其响应于所述一致性目录中的一致性损坏的检测，以动态地修改所选择的一致性算法，从而使所述处理系统能够以受控的方式关闭。 在一些实施例中，监视电路还检测相干目录外的可能的系统一致性故障条件，并且一致性控制电路通过动态地修改所选择的一致性算法来响应可能的系统一致性故障条件的检测，从而使处理系统能够关闭 以受控的方式下来。
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公开(公告)号：US5728150A
公开(公告)日：1998-03-17
申请号：US754816
申请日：1996-11-21
CPC分类号： A61F2/07 , A61F2/90 , A61F2/92 , A61F2/95 , A61F2/0077 , A61F2/852 , A61F2/856 , A61F2/954 , A61F2002/826 , A61F2002/8483 , A61F2002/9511 , A61F2210/0076 , A61F2210/0095 , A61F2220/0008 , A61F2220/0016 , A61F2250/0067 , A61N5/1002
摘要： Disclosed is a tubular prosthesis formed by rolling a perforated sheet around a longitudinal axis. Preferably, the prosthesis is self expandable under the radially outwardly directed spring bias of the rolled sheet. The perforations in the sheet are configured to provide throughholes in the wall of the multilayer prosthesis, when the prosthesis is in the implanted diameter within a vessel. The throughholes are configured to facilitate neointimal cell growth, and in a preferred embodiment, to minimize roll bias in the prosthesis as it is expanded from its reduced, insertion diameter to its expanded, implanted diameter. The prosthesis may be used as a graft or a stent.
摘要翻译： 公开了一种通过围绕纵向轴线滚动多孔板而形成的管状假体。 优选地，假体在轧制板的径向向外指向的弹簧偏压下是可自膨的。 当假体处于容器内的植入直径时，片材中的穿孔构造成在多层假体的壁中提供通孔。 通孔构造成促进新内膜细胞生长，并且在优选实施例中，为了最小化假体中的倾斜偏压，当其从其减小的插入直径扩展到其扩张的植入直径时。 假体可以用作移植物或支架。
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5.发明授权Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces 失效具有多个处理器，多个系统总线和多个I / O总线的计算机系统架构，通过多个端口接口连接
公开(公告)号：US5359715A
公开(公告)日：1994-10-25
申请号：US760786
申请日：1991-09-16
申请人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
发明人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
IPC分类号： G06F15/16 , G06F13/24 , G06F13/36 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.
摘要翻译： 多处理器系统被配置为包括至少两个系统或存储器总线，其中至少两个处理器耦合到每个系统总线，以及耦合到系统总线的至少两个I / O总线，以提供多个扩展槽， 为每个I / O总线以单个系统总线负载为代价的系统的相应数量的I / O总线代理。 系统和I / O总线中的每一个被独立地仲裁以定义用于本发明的多个处理器系统的解耦总线系统。 用于系统的主存储器由至少两个存储器交错组成，每个存储器交错可以通过系统总线同时访问。 每个I / O总线通过I / O接口电路连接到系统总线，I / O接口电路缓冲写入主存储器的数据或由I / O总线代理器读取存储器交错的数据。
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6.发明授权Method and apparatus for decoding bus master arbitration levels to optimize memory transfers 失效用于解码总线主控仲裁级别以优化存储器传输的方法和装置
公开(公告)号：US5327540A
公开(公告)日：1994-07-05
申请号：US16652
申请日：1993-02-01
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.
摘要翻译： 一种用于在计算机系统内优化配置数据缓冲器的缓冲器管理方案，其包括通过微通道总线连接的多个总线主机和数据缓冲器到诸如存储器之类的共享资源。 该方案解码分配给总线主机的唯一的四位微通道仲裁值，以检索存储在每个总线主机的不同配置参数的寄存器文件中的缓冲区配置参数。 根据从寄存器文件检索的参数数据，数据缓冲区被动态地配置为具有最佳性能，每个总线主机具有对微通道总线的控制。
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7.发明授权System and method for terminating lock-step sequences in a multiprocessor system 失效用于在多处理器系统中终止锁步序列的系统和方法公开(公告)号：US06560682B1
公开(公告)日：2003-05-06
申请号：US08943676
申请日：1997-10-03
IPC分类号： G06F1200
CPC分类号： G06F11/0793 , G06F9/52 , G06F11/0724 , G06F13/1663
摘要： There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.
摘要翻译： 提供了一种用于包含耦合到主存储器的多个处理器的处理系统中的控制电路，用于扰乱从处理器接收到的锁步骤序列的存储器请求。 控制电路包括存储器请求发生器，用于产生至少一个可操作以终止锁定步骤序列的存储器请求的存储器请求。
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公开(公告)号：US6090136A
公开(公告)日：2000-07-18
申请号：US881956
申请日：1997-06-25
申请人： Edward A. McDonald , Joe W. Young , Michael Henson
发明人： Edward A. McDonald , Joe W. Young , Michael Henson
CPC分类号： A61F2/07 , A61F2/90 , A61F2/92 , A61F2/962 , A61F2/0077 , A61F2/856 , A61F2/954 , A61F2002/826 , A61F2002/8483 , A61F2002/9517 , A61F2210/0076 , A61F2210/0095 , A61F2250/0067 , A61N2005/1004 , A61N5/1002
摘要： Disclosed is a tubular prosthesis formed by rolling a flexible sheet around a longitudinal axis. Preferably, the prosthesis is self expandable under the radially outwardly directed spring bias of the rolled sheet. Also disclosed are catheters for delivering two or more of the tubular prostheses at a site within a body lumen. Multiple prostheses may be deployed directly against a vessel wall in a single procedure, or may be deployed within a vascular graft to provide support throughout the length of the graft.
摘要翻译： 公开了一种通过围绕纵向轴线滚动柔性片而形成的管状假体。 优选地，假体在轧制板的径向向外指向的弹簧偏压下是可自膨的。 还公开了用于在体腔内的位置处递送两个或更多个管状假体的导管。 多个假体可以在单个过程中直接部署在血管壁上，或者可以部署在血管移植物内以在移植物的整个长度上提供支撑。
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公开(公告)号：US6012127A
公开(公告)日：2000-01-04
申请号：US989371
申请日：1997-12-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.
摘要翻译： 一种多处理器计算装置，包括多个处理器，每个处理器具有高速缓冲存储器，并且优选地布置在系统总线上的节点中。 耦合到处理器的第一高速缓存一致性提供机制，用于实现系统级高速缓存一致性。 还提供了第二高速缓存一致性提供机制。 当在第一高速缓存一致性提供机制中检测到错误时，该机制被禁用，并且由第二高速缓存一致性提供机制实现高速缓存一致性。 在优选实施例中，第一机制包括相干目录，第二机制包括总线监听。
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10.发明授权System for determining the average latency of pending pipelined or split transaction requests through using two counters and logic divider 失效用于通过使用两个计数器和逻辑除法器确定未决流水线或拆分事务请求的平均延迟的系统
公开(公告)号：US5919268A
公开(公告)日：1999-07-06
申请号：US925982
申请日：1997-09-09
申请人： Edward A. McDonald
发明人： Edward A. McDonald
CPC分类号： G06F11/349 , G06F11/3409 , G06F2201/87 , G06F2201/88
摘要： Logic for determining the average latency of pending pipelined and split bus transactions within a computer system including a bus, such as an Intel Pentium Pro or P6 bus, which supports pipelined and split bus transactions. The logic includes a first counter connected to the bus, and containing a TOTAL QUALIFIED CYCLES count value which is incremented on the start of every qualified bus cycle placed on the bus; logic for determining a cycle COUNT-BY-VALUE representing the number of outstanding or pending qualified bus cycles during any bus cycle; and a second counter which is incremented at the start of every qualified bus cycle occurring during the sample period by the number of outstanding qualified bus cycles to provide a TOTAL LATENCY CLOCKS count value. Divider logic is connected to receive the TOTAL QUALIFIED CYCLES count value from the first counter and the TOTAL LATENCY CLOCKS value from the second counter and divide the TOTAL QUALIFIED CYCLES count value into the TOTAL LATENCY CLOCK value to determine the average number of clocks of latency, or average number of pending bus cycles, per qualified bus cycle.
摘要翻译： 用于确定计算机系统中待处理流水线和拆分总线事务的平均延迟的逻辑，包括支持流水线和分流总线事务的总线，例如Intel Pentium Pro或P6总线。 该逻辑包括连接到总线的第一个计数器，并且包含在总线上放置的每个合格的总线周期开始时递增的总计合格循环计数值; 用于确定周期的逻辑COUNT-BY-VALUE表示在任何总线周期期间未完成或未决的有效总线周期数; 以及第二计数器，其在采样周期内发生的每个合格总线周期开始时递增未完成的合格总线周期数，以提供总计时钟计数值。 分频器逻辑被连接以从第一个计数器接收总计合格循环计数值，并从第二个计数器接收TOTAL LATENCY CLOCKS值，并将TOTAL QUALIFIED CYCLES计数值除以TOTAL LATENCY CLOCK值，以确定延迟的平均时钟数， 或每个合格的总线周期的待处理总线周期的平均数。
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