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    Method of fabricating a semiconductor microstructure
    1.
    发明授权
    Method of fabricating a semiconductor microstructure 有权
    制造半导体微结构的方法

    公开(公告)号：US08026147B2

    公开(公告)日：2011-09-27

    申请号：US12856262

    申请日：2010-08-13

    申请人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

    发明人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

    IPC分类号： H01L21/20

    CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L27/10817 ,  H01L27/10852

    摘要： Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

    摘要翻译： 提供一种制造半导体微结构的方法，该方法包括在半导体衬底上形成下部材料层，该下部材料层包括III族元素的氮化物; 在下部材料层上形成模具材料层; 在所述模具材料层上形成蚀刻掩模，所述蚀刻掩模用于在所述模具材料层中形成结构; 通过使用蚀刻掩模对模具材料层和下部材料层进行各向异性蚀刻; 并对模具材料层和下部材料层进行各向同性蚀刻。

    SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING LOWER AND UPPER DEVICE ISOLATION PATTERNS 审中-公开
    半导体器件，包括下部和上部器件隔离图案

    公开(公告)号：US20110037109A1

    公开(公告)日：2011-02-17

    申请号：US12910552

    申请日：2010-10-22

    申请人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

    发明人： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

    IPC分类号： H01L29/68

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

    摘要翻译： 在一些实施例中，半导体衬底包括限定有源区的沟槽。 半导体器件还包括设置在沟槽中的下部和上部器件隔离图案。 栅极绝缘图案和控制栅电极设置在半导体衬底上以跨越有源区。 电荷存储电极位于控制栅电极和有源区之间。 栅极绝缘图案位于电荷存储电极和有源区之间，并且栅间绝缘图案直接接触有源区之间的上部器件隔离图案。

    Semiconductor device isolation structures and methods of fabricating such structures
    3.
    发明授权
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US07674685B2

    公开(公告)日：2010-03-09

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Semiconductor device having trench isolation region and methods of fabricating the same
    4.
    发明申请
    Semiconductor device having trench isolation region and methods of fabricating the same 有权
    具有沟槽隔离区域的半导体器件及其制造方法

    公开(公告)号：US20090020847A1

    公开(公告)日：2009-01-22

    申请号：US12216820

    申请日：2008-07-11

    申请人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    发明人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

    摘要翻译： 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

    Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate
    6.
    发明授权
    Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate 有权
    制造闪存器件的方法包括在暴露的控制栅极的上表面和侧表面上形成硅化物

    公开(公告)号：US08043914B2

    公开(公告)日：2011-10-25

    申请号：US12629920

    申请日：2009-12-03

    申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

    发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

    摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

    Semiconductor device isolation structures and methods of fabricating such structures
    9.
    发明申请
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US20080014711A1

    公开(公告)日：2008-01-17

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Method of manufacturing a non-volatile semiconductor device
    10.
    发明申请
    Method of manufacturing a non-volatile semiconductor device 审中-公开
    制造非易失性半导体器件的方法

    公开(公告)号：US20070004139A1

    公开(公告)日：2007-01-04

    申请号：US11474428

    申请日：2006-06-26

    申请人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

    发明人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L21/7624 ,  H01L27/11521

    摘要： In a method of manufacturing a non-volatile semiconductor device, a mask structure is formed on a substrate. A trench is formed by partially etching the substrate using the mask structure. A preliminary isolation layer pattern is formed on the substrate to fill the trench. The preliminary isolation layer has an upper face lower than that of the mask structure. A capping layer pattern is formed on the preliminary isolation layer pattern. An opening and an isolation layer pattern are formed by removing the mask structure and a portion on a sidewall of the preliminary isolation layer pattern adjacent to the mask structure. After forming a tunnel oxide layer, a floating gate is formed on the tunnel oxide layer and a sidewall of the isolation layer pattern.

    摘要翻译： 在制造非挥发性半导体器件的方法中，在衬底上形成掩模结构。 通过使用掩模结构部分地蚀刻衬底来形成沟槽。 在衬底上形成初步隔离层图形以填充沟槽。 预备隔离层的上表面比掩模结构的上面低。 在初步隔离层图案上形成覆盖层图案。 通过去除掩模结构和邻近掩模结构的预隔离层图案的侧壁上的部分形成开口和隔离层图案。 在形成隧道氧化物层之后，在隧道氧化物层和隔离层图案的侧壁上形成浮栅。