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    Measure of analysis performed in property checking
    3.
    发明授权
    Measure of analysis performed in property checking 有权
    在财产检查中进行的分析测量

    公开(公告)号：US08418121B2

    公开(公告)日：2013-04-09

    申请号：US13027090

    申请日：2011-02-14

    申请人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    发明人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/50 ,  G06F17/504

    摘要： The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

    摘要翻译： 在确定数字电路的属性的有效性时执行的分析量与分析的性能同时测量，并且当不能提供真/假答案时被提供作为输出。 由于资源限制而停止。 在一些实施例中，值N的度量表示在从分析开始的初始状态开始的距离N内不会违反正在检查的给定属性。 因此，在这样的实施例中，值N的度量表示分析已经从初始状态隐含或明确地覆盖了长度N的每个可能的偏移，并且正式证明在该长度N内没有反例。

    Measure of analysis performed in property checking
    4.
    发明授权
    Measure of analysis performed in property checking 有权
    在财产检查中进行的分析测量

    公开(公告)号：US07890897B2

    公开(公告)日：2011-02-15

    申请号：US11939485

    申请日：2007-11-13

    申请人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    发明人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/50 ,  G06F17/504

    摘要： The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

    摘要翻译： 在确定数字电路的属性的有效性时执行的分析量与分析的性能同时测量，并且当不能提供真/假答案时被提供作为输出。 由于资源限制而停止。 在一些实施例中，值N的度量表示在从分析开始的初始状态开始的距离N内不会违反正在检查的给定属性。 因此，在这样的实施例中，值N的度量表示分析已经从初始状态隐含地或明确地覆盖了长度N的每个可能的偏移，并且正式证明在该长度N内没有可能的对比示例。

    Selection of initial states for formal verification
    5.
    发明授权
    Selection of initial states for formal verification 有权
    选择正式验证的初始状态

    公开(公告)号：US07454324B1

    公开(公告)日：2008-11-18

    申请号：US10340500

    申请日：2003-01-10

    申请人： James Andrew Garrard Seawright ,  Ramesh Sathianathan ,  Christophe G. Gauthron ,  Jeremy R. Levitt ,  Kalyana C. Mulam ,  Chian-Min Richard Ho ,  Ping Fai Yeung

    发明人： James Andrew Garrard Seawright ,  Ramesh Sathianathan ,  Christophe G. Gauthron ,  Jeremy R. Levitt ,  Kalyana C. Mulam ,  Chian-Min Richard Ho ,  Ping Fai Yeung

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G06F17/504

    摘要： A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.

    摘要翻译： 计算机被编程为自动选择在模拟期间被访问的数字电路的状态或一组状态，用作形式验证工具的一个或多个初始状态。 这种自动选择一个或多个模拟状态将所有模拟状态的集合减少到小的子集，从而解决状态空间爆炸问题。 根据实施例，编程的计算机使用由库和/或由用户提供的一个或多个标准来进行状态的选择。 这样的标准可以基于数字电路的属性（断言/检验器）和/或在仿真期间产生的信号。 此外，在应用这些标准（也称为“主要标准”）之后，可以在形式分析之前通过应用附加标准（也称为“次要标准”）来修剪所选择的状态。

    Metastability injector for a circuit description
    6.
    发明授权
    Metastability injector for a circuit description 有权
    Metastability注射器用于电路描述

    公开(公告)号：US07243322B1

    公开(公告)日：2007-07-10

    申请号：US10859055

    申请日：2004-06-01

    申请人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    发明人： Tai An Ly ,  Ka Kei Kwok ,  Vijaya Vardhan Gupta ,  Ross Andrew Ander ,  Ping Fai Yeung ,  Neil Patrick Hand ,  Lawrence Curtis Widdoes, Jr.

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5022 ,  G01R31/30

    摘要： During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

    摘要翻译： 在验证包含预定断言的电路的描述期间，为了检测可能由在电路中交叉时钟域（“CDC”信号）的信号中发生的亚稳态引起的电路的不正确行为，描述 该电路通过添加电路自动转换，以将亚稳态的影响注入到CDC信号中。 以正常方式验证包含注入亚稳态的电路的变换描述。 某些实施例使用模型检查方法分析变换的描述，以确定将导致预定的断言被违反的刺激序列。 在一些实施例中，使用来自模型检查的刺激序列来模拟变换电路，并且显示由于亚稳态引起的电路的错误行为，以供电路设计者进行诊断。 电路设计者可以修改电路描述并如上所述进行迭代。

    Measure of analysis performed in property checking
    9.
    发明授权
    Measure of analysis performed in property checking 有权
    在财产检查中进行的分析测量

    公开(公告)号：US06848088B1

    公开(公告)日：2005-01-25

    申请号：US10174379

    申请日：2002-06-17

    申请人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    发明人： Jeremy Rutledge Levitt ,  Christophe Gauthron ,  Chian-Min Richard Ho ,  Ping Fai Yeung ,  Kalyana C. Mulam ,  Ramesh Sathianathan

    IPC分类号： G06F7/60 ,  G06F9/45 ,  G06F17/10 ,  G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/50 ,  G06F17/504

    摘要： The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicated that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

    摘要翻译： 在确定数字电路的属性的有效性时执行的分析量与分析的性能同时测量，并且当不能提供真/假答案时被提供作为输出。 由于资源限制而停止。 在一些实施例中，值N的度量表示在从分析开始的初始状态开始的距离N内不会违反正在检查的给定属性。 因此，在这样的实施例中，值N的度量表明分析已经隐含或明确地覆盖了从初始状态的长度N的每个可能的偏移，并且正式证明在该长度N内没有可能的对比示例。

    PANORAMIC VIRTUAL REALITY FRAMEWORK PROVIDING A DYNAMIC USER EXPERIENCE
    10.
    发明申请
    PANORAMIC VIRTUAL REALITY FRAMEWORK PROVIDING A DYNAMIC USER EXPERIENCE 审中-公开

    公开(公告)号：US20200236278A1

    公开(公告)日：2020-07-23

    申请号：US16749862

    申请日：2020-01-22

    申请人： Fai Yeung ,  Ling Yao ,  Sankar Jayaram ,  Uma Jayaram ,  Ritesh Kale ,  Ok Joon Kim ,  Shaun Carrigan

    发明人： Fai Yeung ,  Ling Yao ,  Sankar Jayaram ,  Uma Jayaram ,  Ritesh Kale ,  Ok Joon Kim ,  Shaun Carrigan

    IPC分类号： H04N5/232 ,  H04N5/262 ,  H04N5/272 ,  G06T19/00

    摘要： An apparatus, system, and method are described for providing real-time capture, processing, and distribution of panoramic virtual reality (VR) content of a live event. One or more triggering events are identified and used to generate graphics and/or audio on client VR devices. For example, one embodiment of a method comprises: capturing video of an event at an event venue with a plurality of cameras to produce a corresponding plurality of video streams; generating a virtual reality (VR) stream based on the plurality of video streams; transmitting the VR stream to a plurality of client VR devices, wherein the client VR devices are to render VR environments based on the VR stream; detecting a triggering event during the event; and transmitting an indication of the triggering event to the plurality of client VR devices, wherein a first client VR device is to generate first event-based graphics and/or first event-based audio in accordance with the indication.