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1.发明授权公开(公告)号：US07653890B2
公开(公告)日：2010-01-26
申请号：US11096469
申请日：2005-04-01
申请人： Chi-Ming Tsai , Lai-Chee Man , Yao-Ting Wang , Fang-Cheng Chang
发明人： Chi-Ming Tsai , Lai-Chee Man , Yao-Ting Wang , Fang-Cheng Chang
CPC分类号： G03F1/36
摘要： A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.
摘要翻译： 描述了一种晶片图像建模和预测系统（“WIMAPS”），其包括在集成电路（“IC”）制造中生成和/或应用分辨率增强技术（“RET”）和印刷过程的模型的系统和方法。 WIMAPS提供了设计人员在预测RET和晶片印刷过程中使用的有效过程，以便设计人员可以在将RET和印刷工艺应用于电路设计之前过滤预测印刷硅轮廓。
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2.发明申请公开(公告)号：US20050268256A1
公开(公告)日：2005-12-01
申请号：US11096469
申请日：2005-04-01
申请人： Chi-Ming Tsai , Lai-Chee Man , Yao-Ting Wang , Fang-Cheng Chang
发明人： Chi-Ming Tsai , Lai-Chee Man , Yao-Ting Wang , Fang-Cheng Chang
CPC分类号： G03F1/36
摘要： A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design
摘要翻译： 描述了一种晶片图像建模和预测系统（“WIMAPS”），其包括在集成电路（“IC”）制造中生成和/或应用分辨率增强技术（“RET”）和印刷过程的模型的系统和方法。 WIMAPS提供了设计人员在预测RET和晶片印刷过程中使用的有效过程，以便设计人员可以在将RET和印刷工艺应用于电路设计之前过滤预测印刷硅轮廓
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公开(公告)号：US20060242618A1
公开(公告)日：2006-10-26
申请号：US11354398
申请日：2006-02-14
申请人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
发明人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705 , G06F17/5081
摘要： Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.
摘要翻译： 提供了用于编程和运行GPU上光刻仿真的仿真引擎的系统和方法。 光刻模拟的这种集成包括在一个或多个GPU上托管各种光刻技术中的任何一种，包括例如分辨率增强技术，光学邻近校正，光学规则检查或光刻检查以及基于模型的DRC，其中操作 一个或多个技术并行运行。 所提供的系统和方法还包括将平版印刷几何操作集成到GPU中以获得改进的性能。 这种集成的示例包括设计规则检查器（DRC），寄生提取，以及放置和路由。
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公开(公告)号：US06904587B2
公开(公告)日：2005-06-07
申请号：US10327446
申请日：2002-12-20
申请人： Chi-Ming Tsai , Chin-Hsen Lin , Yao-Ting Wang
发明人： Chi-Ming Tsai , Chin-Hsen Lin , Yao-Ting Wang
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/68
摘要： A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.
摘要翻译： 光刻掩模布局被设计和逐步验证，以帮助减少产生掩模布局的时间量。 对于一个实施例，可以处理定义目标图案的布局以产生掩模布局，并且可以验证掩模布局以识别错误。 不是通过在一个或多个后续迭代处理和验证整个掩模布局进行纠错，而是可以从掩模布局去除或复制具有错误的子布局以进行单独的处理和验证。 由于定义子布局的数据量相对较小，所以减少了设计和验证掩码布局的时间。 然后，可以使用具有一个或多个经处理和验证的子布局的所得到的掩模布局来制造掩模组，以帮助例如在制造集成电路（IC）中打印目标图案。
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公开(公告)号：US07523027B2
公开(公告)日：2009-04-21
申请号：US10878847
申请日：2004-06-28
IPC分类号： G06F17/50
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
摘要翻译： 提供了一种用于检查用于缺陷的光刻掩模的方法和装置。 检查方法包括向图像模拟器提供缺陷区域图像，其中缺陷区域图像是光刻掩模的一部分的图像，并且提供一组光刻参数作为图像模拟器的第二输入。 缺陷区域图像可以由检查工具提供，该检查工具使用高分辨率显微镜扫描光刻掩模以获得缺陷，并捕获围绕所识别的潜在缺陷的掩模区域的图像。 图像模拟器响应于缺陷区域图像和光刻参数集合而生成第一模拟图像。 第一模拟图像是如果将晶片暴露于通过该掩模的该部分的照明源而将被印刷在晶片上的图像的模拟。 该方法还可以包括提供第二模拟图像，其是对应于由缺陷区域图像表示的部分的设计掩模的部分的晶片印刷的模拟。 该方法还提供了第一和第二模拟图像的比较，以便确定光刻掩模上任何识别的潜在缺陷的可印刷性。 还提供了确定任何识别的潜在缺陷的过程窗口效应的方法。
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公开(公告)号：US07107571B2
公开(公告)日：2006-09-12
申请号：US09906920
申请日：2001-07-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06T7/0004 , G06T2207/30148
摘要： A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.
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公开(公告)号：US06721928B2
公开(公告)日：2004-04-13
申请号：US10323565
申请日：2002-12-17
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.
摘要翻译： 本发明使用基于实例的（IB）表示来减少验证从参考布局生成的经转换的布局所需的时间。 具体来说，从参考布局生成基于IB的表示。 基于IB的表示包括包括主实例单元和从实例单元的实例单元的集合。 需要模拟每组实例单元的一个子集，以验证转换后的布局。
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公开(公告)号：US07216320B2
公开(公告)日：2007-05-08
申请号：US10984443
申请日：2004-11-08
申请人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
发明人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.
摘要翻译： 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。
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9.发明授权Method and apparatus for exposing a wafer using multiple masks during an integrated circuit manufacturing process 有权在集成电路制造过程中使用多个掩模曝光晶片的方法和装置公开(公告)号：US06795168B2
公开(公告)日：2004-09-21
申请号：US10117838
申请日：2002-04-08
IPC分类号： G03B2754
CPC分类号： G03F7/70208 , G03F7/70283
摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.
摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。
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公开(公告)号：US06757645B2
公开(公告)日：2004-06-29
申请号：US09130996
申请日：1998-08-07
IPC分类号： G06F1750
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
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