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    FERROELECTRIC CAPACITIVE MEMORY DEVICES WITH A MULTIPLE-WORK-FUNCTION ELECTRODE
    1.
    发明申请
    FERROELECTRIC CAPACITIVE MEMORY DEVICES WITH A MULTIPLE-WORK-FUNCTION ELECTRODE 有权

    公开(公告)号：US20250151369A1

    公开(公告)日：2025-05-08

    申请号：US18501170

    申请日：2023-11-03

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Xinshu Cai ,  Shyue Seng Tan

    IPC: H01L29/51 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H10B53/30

    Abstract: Structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device. The structure comprises a first electrode including a first doped region in a semiconductor layer and a second doped region in the semiconductor layer, an interconnection that is configured to connect the first doped region to the second doped region, a ferroelectric layer on the semiconductor layer, and a second electrode including a first section and a second section on the ferroelectric layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material.

    Programmable interposer using RRAM platform
    2.
    发明授权
    Programmable interposer using RRAM platform 有权

    公开(公告)号：US12284924B2

    公开(公告)日：2025-04-22

    申请号：US17697974

    申请日：2022-03-18

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San Leong ,  Juan Boon Tan ,  Benfu Lin ,  Yi Jiang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

    ANTIFUSES CAPABLE OF FORMING LOCALIZED CONDUCTIVE LINKS
    3.
    发明申请
    ANTIFUSES CAPABLE OF FORMING LOCALIZED CONDUCTIVE LINKS 有权

    公开(公告)号：US20250113483A1

    公开(公告)日：2025-04-03

    申请号：US18479816

    申请日：2023-10-02

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： ZAR LWIN ZIN ,  SHYUE SENG TAN ,  ENG HUAT TOH

    IPC: H10B20/25

    Abstract: The embodiments herein relate to antifuses capable of forming localized conductive links and methods of forming the same. An antifuse is provided. The antifuse includes a substrate, a dielectric liner, and an electrode. The substrate includes a conductor layer, and a trench is in the conductor layer. The trench includes a first conductor surface and a second conductor surface. The dielectric liner is in the trench. The electrode is on the dielectric liner in the trench, and the electrode includes a first electrode surface and a second electrode surface converging to the first electrode surface.

    RESISTIVE MEMORY ELEMENTS WITH A MULTIPLE-MATERIAL ELECTRODE
    7.
    发明申请
    RESISTIVE MEMORY ELEMENTS WITH A MULTIPLE-MATERIAL ELECTRODE 有权

    公开(公告)号：US20250057058A1

    公开(公告)日：2025-02-13

    申请号：US18232868

    申请日：2023-08-11

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Curtis Chun-I Hsieh ,  Kai Kang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode includes a first metal feature and a second metal feature inside the first metal feature. The first metal feature comprising a first metal, and the second metal feature comprises a second metal with a different composition than the first metal. The first metal feature adjoins a first portion of the switching layer, and the second metal feature adjoins a second portion of the switching layer.

    Lateral multi-bit memory devices and methods of making the same
    8.
    发明授权
    Lateral multi-bit memory devices and methods of making the same 有权

    公开(公告)号：US12193243B2

    公开(公告)日：2025-01-07

    申请号：US17650084

    申请日：2022-02-07

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Desmond Jia Jun Loy ,  Eng Huat Toh ,  Shyue Seng Tan

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

    Field-effect transistors with airgap spacers
    9.
    发明授权
    Field-effect transistors with airgap spacers 有权

    公开(公告)号：US12176405B1

    公开(公告)日：2024-12-24

    申请号：US18664386

    申请日：2024-05-15

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Khee Yong Lim ,  Xinfu Liu ,  Xiao Mei Elaine Low

    IPC: H01L29/417 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

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