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公开(公告)号：US12096622B2
公开(公告)日：2024-09-17
申请号：US17502140
申请日：2021-10-15
IPC分类号： H10B41/20 , B82Y10/00 , B82Y40/00 , H10B41/23 , H10B41/27 , H10B41/41 , H10B43/20 , H10B43/23 , H10B43/27 , H10B43/40
摘要： A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.
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公开(公告)号：US20240244841A1
公开(公告)日：2024-07-18
申请号：US18618675
申请日：2024-03-27
申请人： SK hynix Inc.
发明人： Nam Jae LEE
摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other; and a source contact structure extending into the stack structure in a vertical direction to be coupled to the source structure, wherein the source contact structure includes polysilicon.
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公开(公告)号：US20240155843A1
公开(公告)日：2024-05-09
申请号：US17994401
申请日：2022-11-28
发明人： Wang Xiang , CHIA CHING HSU , Shen-De Wang , Yung-Lin Tseng , WEICHANG LIU
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11553 , H01L27/1158
摘要： A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
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公开(公告)号：US20240172449A1
公开(公告)日：2024-05-23
申请号：US18422245
申请日：2024-01-25
发明人： Sheng-Chih Lai , Chung-Te Lin
IPC分类号： H10B51/30 , H10B41/23 , H10B41/27 , H10B41/35 , H10B43/23 , H10B51/20 , H10B51/40 , H10B51/50
CPC分类号： H10B51/30 , H10B41/23 , H10B41/27 , H10B41/35 , H10B43/23 , H10B51/20 , H10B51/40 , H10B51/50
摘要： Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.
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公开(公告)号：US11942553B2
公开(公告)日：2024-03-26
申请号：US17124692
申请日：2020-12-17
IPC分类号： H01L29/786 , H01L29/66 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/60 , H10B41/70 , H10B43/23 , H10B43/27 , H10B51/20 , H10B53/20 , H10B63/00
CPC分类号： H01L29/7869 , H01L29/66757 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/60 , H10B41/70 , H10B43/23 , H10B43/27 , H10B51/20 , H10B53/20 , H10B63/84 , H10B63/845
摘要： The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.
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公开(公告)号：US11889697B2
公开(公告)日：2024-01-30
申请号：US17900429
申请日：2022-08-31
申请人： SK hynix Inc.
发明人： Nam Jae Lee
摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.
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7.发明申请公开(公告)号：US20230134659A1
公开(公告)日：2023-05-04
申请号：US18090357
申请日：2022-12-28
发明人： Liang Chen
摘要： The present disclosure provides a semiconductor device, a three-dimensional memory and a fabrication method of the semiconductor device. The semiconductor device comprises a substrate, a plurality of gates on a first side of the substrate and extending parallelly in a first horizontal direction, a plurality of first contacts each on a corresponding one of the plurality of gates and extending along the first horizontal direction, and a plurality of second contacts on the first side of the substrate, each second contact extends along the first horizontal direction, and is located between adjacent two first contacts and between two corresponding gates.
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公开(公告)号：US20240250180A1
公开(公告)日：2024-07-25
申请号：US18586255
申请日：2024-02-23
IPC分类号： H01L29/786 , H01L29/66 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/60 , H10B41/70 , H10B43/23 , H10B43/27 , H10B51/20 , H10B53/20 , H10B63/00
CPC分类号： H01L29/7869 , H01L29/66757 , H10B41/20 , H10B41/23 , H10B41/27 , H10B41/60 , H10B41/70 , H10B43/23 , H10B43/27 , H10B51/20 , H10B53/20 , H10B63/84 , H10B63/845
摘要： The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.
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公开(公告)号：US12022651B2
公开(公告)日：2024-06-25
申请号：US17406228
申请日：2021-08-19
发明人： Hung-Shu Huang , Ming Chyi Liu
CPC分类号： H10B41/27 , G11C16/0416 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H10B43/23
摘要： The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.
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公开(公告)号：US20240147714A1
公开(公告)日：2024-05-02
申请号：US18404086
申请日：2024-01-04
发明人： Hung-Shu Huang , Ming Chyi Liu
IPC分类号： H10B41/27 , G11C16/04 , H01L29/423 , H01L29/66 , H10B43/23
CPC分类号： H10B41/27 , G11C16/0416 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H10B43/23
摘要： The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.
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