公开(公告)号：US11744085B2

公开(公告)日：2023-08-29

申请号：US17016416

申请日：2020-09-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Yi Jiang ,  Lup San Leong ,  Juan Boon Tan

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  G11C13/0002 ,  G11C13/0021 ,  H10N70/20 ,  H10N70/231

Abstract: A semiconductor device includes a first insulating layer; a second insulating layer arranged over the first insulating layer; a memory structure arranged within a memory region and including a resistance changing memory element within the first insulating layer; and a logic structure arranged within a logic region. In the memory region, the first insulating layer may contact the second insulating layer and in the logic region, the semiconductor device may further include a stop layer arranged between the first insulating layer and the second insulating layer.

公开(公告)号：US09242338B2

公开(公告)日：2016-01-26

申请号：US14059448

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

IPC: B24B49/16 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

公开(公告)号：US11164858B2

公开(公告)日：2021-11-02

申请号：US16816365

申请日：2020-03-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Bo Yu ,  Chim Seng Seet ,  Kin Wai Tang

IPC: H01L21/00 ,  H01L27/01 ,  H01L21/70 ,  H01L49/02

Abstract: According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

公开(公告)号：US09511470B2

公开(公告)日：2016-12-06

申请号：US15005034

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

IPC: B24B37/005 ,  B24B49/16 ,  B24B37/32

CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

公开(公告)号：US09242341B2

公开(公告)日：2016-01-26

申请号：US14059451

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wei Lu ,  Alex See

IPC: B24B49/00 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器和用于根据保持环与其膜之间的台阶高度来调节保持环的运动的控制器，以确保台阶高度保持在固定值，作为保持 戒指磨损了。

公开(公告)号：US11600664B2

公开(公告)日：2023-03-07

申请号：US16744223

申请日：2020-01-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Eng Huat Toh ,  Benfu Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

公开(公告)号：US11522131B2

公开(公告)日：2022-12-06

申请号：US16945058

申请日：2020-07-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Wanbing Yi ,  Benfu Lin ,  Cing Gie Lim ,  Wei-Hui Hsu ,  Juan Boon Tan

IPC: H01L45/00 ,  H01L21/306 ,  H01L27/24

Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.

公开(公告)号：US11335635B2

公开(公告)日：2022-05-17

申请号：US16842956

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Benfu Lin ,  Kah Wee Gan ,  Cing Gie Lim ,  Chengang Feng

IPC: H01L23/522 ,  H01L25/04

Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

公开(公告)号：US09711662B1

公开(公告)日：2017-07-18

申请号：US15134542

申请日：2016-04-21

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Shunqiang Gong ,  Benfu Lin ,  Juan Boon Tan ,  Ramakanth Alapati

IPC: H01L31/02 ,  H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/02002 ,  H01L31/0224 ,  H01L31/02327 ,  H01L31/035281 ,  H01L31/18 ,  Y02E10/50

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.

公开(公告)号：US20220037590A1

公开(公告)日：2022-02-03

申请号：US16945058

申请日：2020-07-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Wanbing Yi ,  Benfu Lin ,  Cing Gie Lim ,  Wei-Hui Hsu ,  Juan Boon Tan

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/306

Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.