公开(公告)号：US08338280B2

公开(公告)日：2012-12-25

申请号：US12832082

申请日：2010-07-08

申请人： Dexter Tan ,  Kin Leong Pey ,  Sai Hooi Yeong ,  Yoke King Chin ,  Kuang Kian Ong ,  Chee Mang Ng

发明人： Dexter Tan ,  Kin Leong Pey ,  Sai Hooi Yeong ,  Yoke King Chin ,  Kuang Kian Ong ,  Chee Mang Ng

IPC分类号： H01L21/425

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/7613

摘要： Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

摘要翻译： 实施例涉及一种用于在纳米器件中制造纳米线的方法，更具体地涉及使用端部范围（EOR）缺陷的纳米器件制造。 在一个实施例中，提供了在衬底上具有表面结晶层的衬底，并且在表面晶体层中产生了EOR缺陷。 一个或多个嵌入有EOR缺陷的翅片被形成并被氧化，以在纳米线芯内形成具有纳米晶体的一个或多个完全氧化的纳米线。

公开(公告)号：US20100124809A1

公开(公告)日：2010-05-20

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 在结晶半导体衬底中形成浅结区域的方法和具有浅结区域的半导体器件的制造方法包括缺陷工程步骤，其中将第一离子引入到衬底的第一区域中，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US20090286373A1

公开(公告)日：2009-11-19

申请号：US12466391

申请日：2009-05-15

申请人： Dexter Xueming TAN ,  Benjamin COLOMBEAU ,  Clark Kuang Kian ONG ,  Sai Hooi YEONG ,  Chee Mang NG ,  Kin Leong PEY

发明人： Dexter Xueming TAN ,  Benjamin COLOMBEAU ,  Clark Kuang Kian ONG ,  Sai Hooi YEONG ,  Chee Mang NG ,  Kin Leong PEY

IPC分类号： H01L21/336 ,  H01L21/322

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

摘要翻译： 本发明提供一种制造半导体器件的方法。 该方法包括提供衬底并在衬底上形成栅叠层。 执行在栅极堆叠的相对侧上在衬底内形成空位丰富区域的第一激光处理。 空位丰富区域具有从基板表面的第一深度。 还执行第一种植入物，其在基板的表面的第二深度处形成在栅叠层的相对侧上形成范围缺陷区域的端部，其中第一深度接近第二深度。

公开(公告)号：US07892905B2

公开(公告)日：2011-02-22

申请号：US11195196

申请日：2005-08-02

申请人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

IPC分类号： H01L31/0216 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的预非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

公开(公告)号：US20120009749A1

公开(公告)日：2012-01-12

申请号：US12832082

申请日：2010-07-08

申请人： Dexter TAN ,  Kin Leong PEY ,  Sai Hooi YEONG ,  Yoke King CHIN ,  Kuang Kian ONG ,  Chee Mang NG

发明人： Dexter TAN ,  Kin Leong PEY ,  Sai Hooi YEONG ,  Yoke King CHIN ,  Kuang Kian ONG ,  Chee Mang NG

IPC分类号： H01L21/335 ,  H01L21/22

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/7613

摘要： Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

摘要翻译： 实施例涉及一种用于在纳米器件中制造纳米线的方法，更具体地涉及使用端部范围（EOR）缺陷的纳米器件制造。 在一个实施例中，提供了在衬底上具有表面结晶层的衬底，并且在表面晶体层中产生了EOR缺陷。 一个或多个嵌入有EOR缺陷的翅片被形成并被氧化，以在纳米线芯内形成具有纳米晶体的一个或多个完全氧化的纳米线。

公开(公告)号：US08101487B2

公开(公告)日：2012-01-24

申请号：US12466391

申请日：2009-05-15

申请人： Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

发明人： Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

摘要翻译： 提出了一种制造半导体器件的方法。 该方法包括提供衬底并在衬底上形成栅叠层。 执行在栅极堆叠的相对侧上在衬底内形成空位丰富区域的第一激光处理。 空位丰富区域具有从基板表面的第一深度。 还执行第一种植入物，其在基板的表面的第二深度处形成在栅堆叠的相对侧上形成范围缺陷区域的端部，其中第一深度接近第二深度。

公开(公告)号：US07888224B2

公开(公告)日：2011-02-15

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 一种在晶体半导体衬底中形成浅结区的方法和用于制造具有浅结区的半导体器件的方法包括：缺陷工程步骤，其中将第一离子引入衬底的第一区域，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。